Flash memory with improved gate structure and a method of creating the same
Various embodiments provide a flash memory with an improved gate structure and a method of creating the same. The flash memory includes a plurality of memory cells that include a memory gate, a selection gate, a gate dielectric layer, and a protective cap formed on an upper surface of the gate dielectric layer. The protective cap protects the gate dielectric layer, and prevents the memory and selection gates from being unintentionally electrically connected to each other by conductive material.
1 . A method, comprising:
forming a first conductive layer on a substrate;
forming a second conductive layer on the substrate;
forming a dielectric layer on the substrate, the dielectric layer including first and second portions on opposite sides of the second conductive layer, the first portion being between the first and second conductive layers;
removing a part of the first portion of the dielectric layer that separates the first and second conductive layers from each other;
removing a part of the second portion of the dielectric layer; and
forming a protective layer on the first portion of the dielectric layer at a position where the part of the first portion of the dielectric layer was removed, and on the second portion of the dielectric layer at a position where the part of the second portion of the dielectric layer was removed, such that uppermost surfaces of the first conductive layer, the second conductive layer, the protective layer over the first portion of the dielectric layer, and the protective layer over the second portion of the dielectric layer are coplanar with each other.
2 . The method of claim 1 wherein forming the dielectric layer includes forming the dielectric layer between the first conductive layer and the substrate and between the second conductive layer and the substrate.
3 . The method of claim 1 , further comprising:
forming a source region in the substrate; and
forming a drain region in the substrate,
the first conductive layer, the second conductive layer, the dielectric layer, and the protective layer being positioned between the source region and the drain region.
4 . The method of claim 1 , wherein forming the dielectric layer includes forming an oxide-nitride-oxide (ONO) layer.
5 . The method of claim 1 , wherein forming the second conductive layer includes:
removing a first portion of the second conductive layer; and
removing a second portion of the second conductive layer, the first and second portions of the second conductive layer being on opposite sides of the first conductive layer.
6 . A method, comprising:
forming a first conductive layer on a substrate;
forming a second conductive layer on the substrate;
forming a dielectric layer on the substrate, the dielectric layer including a first portion between the first conductive layer and the second conductive layer, and a second portion on an opposite side of the second conductive layer from the first portion;
forming a first cavity between the first conductive layer and the second conductive layer by removing a part of the first portion of the dielectric layer between the first conductive layer and the second conductive layer;
forming a second cavity by removing a part of the second portion of the dielectric layer; and
forming a protective layer on the first portion of the dielectric layer and in the first cavity, and on the second portion of the dielectric layer and in the second cavity, such that uppermost surfaces of the first conductive layer, the second conductive layer, the protective layer over the first portion of the dielectric layer, and the protective layer over the second portion of the dielectric layer are coplanar with each other.
7 . The method of claim 6 , further comprising:
forming source and drain regions in the substrate.
8 . The method of claim 6 wherein forming the second conductive layer includes:
removing a first portion of the second conductive layer; and
removing a second portion of the second conductive layer, the first and second portions of the second conductive layer being on opposite sides of the first conductive layer.
9 . The method of claim 6 wherein each of the first cavity and the second cavity has a height that is between 100 and 200 angstrom, and a width that is between 100 and 200 angstrom.
10 . The method of claim 6 wherein forming the dielectric layer includes forming an oxide-nitride-oxide (ONO) layer.
11 . The method of claim 6 , further comprising:
removing a portion of the protective layer that extends past surfaces of the first conductive layer and the second conductive layer.
12 . The method of claim 11 wherein forming the protective layer and removing the portion of the protective layer is a mask-free process.
13 . A method of forming a memory, the method comprising:
forming a conductive memory gate on a substrate;
forming a conductive selection gate on the substrate;
forming a gate dielectric layer having a first portion between the memory gate and the selection gate and a second portion, the first and second portions positioned on opposites sides of the selection gate;
forming a first cavity between the conductive memory gate and the conductive selection gate by removing a part of the first portion of the gate dielectric layer;
forming a second cavity by removing a part of the second portion of the gate dielectric layer;
forming a first protective cap in the first cavity, on the first portion of the gate dielectric layer, and between the conductive memory gate and the conductive selection gate;
forming a second protective cap in the second cavity and on the second portion of the gate dielectric layer; and
removing portions of the first and second protective caps such that a surface of the memory gate, a surface of the selection gate, and surfaces of the first and second protective caps are at a same level with each other.
14 . The method of claim 13 , further comprising:
forming a source region in the substrate; and
forming a drain region in the substrate, the drain region being separated from the source region by the memory gate and the selection gate.
15 . The method of claim 13 wherein the forming of the gate dielectric layer includes forming a plurality of sub-layers.
16 . The method of claim 15 wherein the forming of the plurality of sub-layers includes forming a first oxide layer, forming a second oxide layer, and forming a nitride layer sandwiched between the first oxide layer and the second oxide layer.
17 . The method of claim 13 , further comprising:
forming a first contact layer on the surface of the memory gate; and
forming a second contact layer on the surface of the selection gate.
18 . The method of claim 17 wherein the first contact layer and the second contact layer include nickel silicide.
19 . The method of claim 13 wherein the forming of the gate dielectric layer includes forming the gate dielectric layer between the memory gate and the substrate.
20 . The method of claim 19 wherein the memory gate is smaller than the selection gate.