Semiconductor memory device

1 . A semiconductor memory device comprising:

a source layer including a first surface provided at a first position in a first direction intersecting with the first surface of the source layer, the first surface extending in a second direction intersecting with the first direction and a third direction intersecting with the first direction and the second direction;

a semiconductor layer extending in the first direction;

a first conductive layer stacked above the source layer, extending in the second direction, and opposed to the semiconductor layer;

a second conductive layer stacked above the first conductive layer, extending in the second direction, and opposed to the semiconductor layer;

an electric charge accumulating layer disposed between the semiconductor layer and the first conductive layer, and between the semiconductor layer and the second conductive layer;

a first contact electrode extending in the first direction, including an end in the first direction provided under the first position in the first direction, and connected to the second conductive layer; and

an insulating layer provided between the end in the first direction of the first contact electrode and the source layer,

wherein:

the second conductive layer includes:

a first part opposed to the semiconductor layer; and

a second part connected to the first contact electrode, and

a thickness of the second part in the first direction is greater than a thickness of the first part in the first direction.

2 . The semiconductor memory device according to claim 1 , wherein:

the first contact electrode includes:

a third part extending in the first direction and opposed to the first conductive layer; and

a fourth part connected to the second part of the second conductive layer,

in a first cross-sectional surface parallel to a plane extending in the second direction and the third direction and including the fourth part, the second conductive layer surrounds an outer peripheral surface of the fourth part and is connected to the outer peripheral surface of the fourth part, and

in a second cross-sectional surface parallel to a plane extending in the second direction and the third direction and including the third part, the first conductive layer surrounds an outer peripheral surface of the third part and is spaced apart from the outer peripheral surface of the third part.

3 . The semiconductor memory device according to claim 2 , wherein a width of the first contact electrode in the first cross-sectional surface is the same as or larger than a width of the first contact electrode in the second cross-sectional surface.

4 . The semiconductor memory device according to claim 2 , wherein a width of the first contact electrode in the first cross-sectional surface is smaller than a width of the first contact electrode in the second cross-sectional surface.

5 . The semiconductor memory device according to claim 1 , further comprising:

a second insulating layer extending in the first direction and connected to the first conductive layer,

wherein a width of the second insulating layer in the second direction is greater than a width of the second insulating layer in the third direction.

6 . The semiconductor memory device according to claim 1 , comprising:

a memory region comprising the semiconductor layer, the first conductive layer, and the electric charge accumulation layer; and

a contact region adjacent to the memory region in the second direction,

wherein:

the contact region includes a plurality of columnar structures arranged in the second direction at a predetermined pitch,

each of the plurality of columnar structures extends in the first direction, and

the first contact electrode is one of the plurality of columnar structures.

7 . The semiconductor memory device according to claim 1 , comprising:

a memory region comprising the semiconductor layer, the first conductive layer, and the electric charge accumulation layer; and

a plurality of contact regions adjacent to the memory region in the second direction and arranged in the third direction,

wherein:

each of the plurality of contact regions includes a plurality of columnar structures arranged in the second direction at a predetermined pitch,

each of the plurality of columnar structures extends in the first direction, and

in a first cross-sectional surface extending in the second direction and the third direction, the plurality of columnar structures include:

a first columnar structure;

a second columnar structure adjacent to the first columnar structure in the second direction;

a third columnar structure adjacent to the first columnar structure in a direction of +40° to +80° with respect to the second direction; and

a fourth columnar structure adjacent to the first columnar structure in a direction of −40° to −80° with respect to the second direction.

8 . The semiconductor memory device according to claim 1 , further comprising:

a plurality of second regions and a plurality of third regions alternately arranged in the third direction,

wherein:

the plurality of second regions include a plurality of second contact electrodes arranged in the second direction,

each of the plurality of second contact electrodes extends in the first direction,

the first contact electrode is one of the plurality of second contact electrodes,

the plurality of third regions include a plurality of third insulating layers arranged in the second direction, and

each of the plurality of third insulating layers extends in the first direction.