Semiconductor memory device with improved degree of integration

1 . A semiconductor memory device comprising:

a gate stack structure having a surface extending in a first direction and a second direction, which intersect each other, the gate stack structure including a plurality of conductive patterns disposed to be spaced apart from each other in a third direction intersecting the surface;

a channel structure disposed inside the gate stack structure, the channel structure having a cross-sectional structure including a major axis facing in the first direction and a minor axis facing in the second direction;

a memory layer between the channel structure and the gate stack structure;

two or more bit lines disposed above the gate stack structure, the two or more bit lines extending in a direction intersecting the major axis of the channel structure, the two or more bit lines being arranged to be spaced apart from each other in a direction in which the major axis of the channel structure faces; and

a conductive contact structure connected between one of the two or more bit lines and the channel structure,

wherein the two or more bit lines include a first bit line, a second bit line and a third bit line, and

wherein the first to third bit lines overlap with the channel structure.

2 . The semiconductor memory device of claim 1 ,

wherein the cross-sectional structure of the channel structure has substantially an elliptical shape.

3 . The semiconductor memory device of claim 1 ,

wherein the channel structure overlaps with the two or more bit lines.

4 . The semiconductor memory device of claim 1 ,

wherein the first bit line includes a portion overlapping with a central point of the channel structure and is arranged between the second bit line and the third bit line.

5 . The semiconductor memory device of claim 4 , further comprising an interposition insulating layer disposed between the gate stack structure and the two or more bit lines, the interposition insulating layer being penetrated by the conductive contact structure,

wherein the first bit line is connected to the channel structure by the conductive contact structure, and the second bit line and the third bit line are insulated from the channel structure by the interposition insulating layer.

6 . The semiconductor memory device of claim 1 , further comprising an interposition insulating layer disposed between the gate stack structure and the two or more bit lines, the interposition insulating layer being penetrated by the conductive contact structure,

wherein the first bit line is connected to the channel structure by the conductive contact structure, and the second bit line is insulated from the channel structure by the interposition insulating layer.

7 . A semiconductor memory device comprising:

a gate stack structure having a surface extending in a first direction and a second direction, which intersect each other, the gate stack structure including a plurality of conductive patterns disposed to be spaced apart from each other in a third direction intersecting the surface;

a plurality of channel structures disposed in the first direction and the second direction inside the gate stack structure, the plurality of channel structures having a cross-sectional structure including a major axis facing in the first direction and a minor axis facing in the second direction;

a plurality of memory layers between the plurality of channel structures and the gate stack structure;

a plurality of bit lines disposed above the gate stack structure, the plurality of bit lines being arranged to be spaced apart from each other in a direction in which the major axes of the plurality of channel structures face; and

a plurality of conductive contact structures connecting the plurality of bit lines to the plurality of channel structures,

wherein the plurality of channel structures include a first channel structure,

wherein the plurality of bit lines include a first bit line, a second bit line and a third bit line, and

wherein the first to third bit lines overlap with the first channel structure.

8 . The semiconductor memory device of claim 7 ,

wherein the cross-sectional structure of the plurality of channel structures has substantially an elliptical shape.

9 . The semiconductor memory device of claim 7 ,

wherein the plurality of channel structures are arranged in a zigzag pattern.

10 . The semiconductor memory device of claim 7 ,

wherein the plurality of channel structures further include a second channel structure and a third channel structure, which are arranged in a line in the second direction,

wherein the plurality of bit lines further include a fourth bit line and a fifth bit line

wherein the fourth bit line extends to overlap with the second channel structure,

wherein the fifth bit line extends to overlap with the third channel structure, and

wherein the first bit line is arranged between the fourth bit line and the fifth bit line.

11 . The semiconductor memory device of claim 10 ,

wherein the plurality of conductive contact structures include a first conductive contact structure between the first channel structure and the third bit line, a second conductive contact structure between the second channel structure and the first bit line, and a third conductive contact structure between the third channel structure and the second bit line, and

wherein the first to third conductive contact structures are spaced apart from each other in the first direction and the second direction.

12 . A semiconductor memory device comprising:

a gate stack structure having a surface extending in a first direction and a second direction, which intersect each other, the gate stack structure including a plurality of conductive patterns disposed to be spaced apart from each other in a third direction intersecting the surface;

first to third channel structures disposed inside the gate stack structure, the first to third channel structures having a cross-sectional structure including a major axis facing in the first direction and a minor axis facing in the second direction, the first to third channel structures being arranged substantially at apexes of a triangle;

a memory layer between each of the first to third channel structures and the gate stack structure;

first to third bit lines disposed above the gate stack structure, the first to third bit lines being arranged to be spaced apart from each other in a direction in which the major axis of each of the first to third channel structures faces; and

first to third conductive contact structures connecting the first to third bit lines to the first to third channel structures respectively, and

further comprising a fourth bit line and a fifth bit line, and

wherein the first bit line, the fourth bit line and the fifth bit line overlap with the first channel structure.

13 . The semiconductor memory device of claim 12 ,

wherein the cross-sectional structure of each of the first to third channel structures has substantially an elliptical shape.

14 . The semiconductor memory device of claim 12 ,

wherein the first conductive contact structure and the first bit line are aligned at a central point of the first channel structure,

wherein the second conductive contact structure and the second bit line are aligned at a central point of the second channel structure, and

wherein the third conductive contact structure the third bit line are aligned at a central point of the third channel structure.

15 . The semiconductor memory device of claim 12 ,

wherein the second channel structure and the third channel structure are arranged in a line in the first direction, and

wherein the first channel structure is spaced apart from the second channel structure and the third channel structure in the second direction.

16 . The semiconductor memory device of claim 15 ,

wherein the first bit line overlaps with the central point of the first channel structure, the second bit line overlaps with the central point of the second channel structure, and the third bit line overlaps with the central point of the third channel structure.

17 . The semiconductor memory device of claim 16 ,

wherein the fourth bit line is disposed between the first bit line and the second bit line,

wherein the fourth bit line extends in the second direction to overlap with the second channel structure,

wherein the fifth bit line is disposed between the first bit line and the third bit line, and

wherein the fifth bit line extending in the second direction to overlap with the third channel structure.