Semiconductor device and method of manufacturing the same
A semiconductor device includes a first stacked structure having first conductive layers and first insulating layers formed alternately with each other, first semiconductor patterns passing through the first stacked structure, a coupling pattern coupled to the first semiconductor patterns, and a slit passing through the first stacked structure and the coupling pattern.
1 . A semiconductor device, comprising:
a stacked structure including conductive layers and insulating layers stacked alternately with the conductive layers in a vertical direction;
a plurality of first semiconductor patterns formed through the stacked structure;
a plurality of second semiconductor patterns formed through the stacked structure and spaced apart from the plurality of first semiconductor patterns in a first direction;
coupling patterns overlapping the stacked structure; and
a first slit located between the coupling patterns at a level where the coupling patterns are arranged, the first slit extending in a second direction crossing the first direction,
wherein the first slit extends to pass through the stacked structure between the plurality of first semiconductor patterns and the plurality of second semiconductor patterns,
wherein each of the coupling patterns extends to couple the plurality of first semiconductor patterns to each other in the second direction or to couple the plurality of second semiconductor patterns to each other in the second direction, and
wherein the vertical direction crosses the first direction and the second direction.
2 . The semiconductor device of claim 1 , further comprising an insulating layer formed in the first slit.
3 . The semiconductor device of claim 1 , wherein the stacked structure includes a first stacked structure and a second stacked structure located under the first stacked structure,
wherein each of the first semiconductor patterns includes a first upper semiconductor pattern passing through the first stacked structure and a first lower semiconductor pattern passing through the second stacked structure, and
wherein each of the second semiconductor patterns includes a second upper semiconductor pattern passing through the first stacked structure and a second lower semiconductor pattern passing through the second stacked structure.
4 . The semiconductor device of claim 3 , wherein the coupling patterns include a first coupling pattern disposed between the first upper semiconductor pattern and the first lower semiconductor pattern and a second coupling pattern disposed between the second upper semiconductor pattern and the second lower semiconductor pattern, and
wherein the first slit is disposed between the first coupling pattern and the second coupling pattern and extends between the first upper semiconductor pattern and the second upper semiconductor pattern and between the first lower semiconductor pattern and the second lower semiconductor pattern.
5 . The semiconductor device of claim 4 , wherein the first coupling pattern, the first upper semiconductor pattern and the first lower semiconductor pattern are connected to each other to form a first channel layer, and
wherein the second coupling pattern, the second upper semiconductor pattern and the second lower semiconductor pattern are connected to each other to form a second channel layer.
6 . The semiconductor device of claim 1 , wherein the coupling patterns include a first coupling pattern coupled to the plurality of first semiconductor patterns and a second coupling pattern coupled to the plurality of second semiconductor patterns.
7 . The semiconductor device of claim 6 , wherein the first coupling pattern includes a sidewall protruding farther than a sidewall of each of the first semiconductor patterns in a lateral direction, and
wherein the second coupling pattern includes a sidewall protruding farther than a sidewall of each of the second semiconductor patterns in the lateral direction.
8 . The semiconductor device of claim 1 , wherein a memory block includes the plurality of first semiconductor patterns and the plurality of second semiconductor patterns.
9 . The semiconductor device of claim 1 , further comprising a multilayer dielectric layer surrounding a sidewall of the plurality of first semiconductor patterns and the plurality of second semiconductor patterns.
10 . The semiconductor device of claim 9 , wherein the multilayer dielectric layer includes a tunnel insulating layer, a data storage layer and a charge blocking layer.
11 . The semiconductor device of claim 1 ,
wherein sidewalls of the coupling patterns are formed along the first slit.
12 . The semiconductor device of claim 1 , further comprising:
a plurality of third semiconductor patterns formed through the stacked structure; and
a second slit to pass through the stacked structure between the plurality of second semiconductor patterns and the plurality of third semiconductor patterns,
wherein the second slit is spaced apart from the coupling patterns.
13 . A semiconductor device, comprising:
a first stack including first conductive layers and first insulating layers that are alternately stacked;
a second stack including second conductive layers and second insulating layers that are alternately stacked and adjacent to the first stack in a first direction;
a first coupling pattern under the first stack and extending in a second direction crossing the first direction;
a second coupling pattern under the second stack, wherein the second coupling pattern is adjacent to the first coupling pattern in the first direction and extends in the second direction;
first semiconductor patterns extending through the first stack;
second semiconductor patterns extending through the second stack; and
a slit insulating layer disposed between the first coupling pattern and the second coupling pattern and between the first stack and the second stack,
wherein the first coupling pattern is coupled to at least two of the first rows of the first semiconductor patterns, and
wherein each of the first rows includes first semiconductor patterns arranged in the second direction.
14 . The semiconductor device of claim 13 , wherein the second coupling pattern is coupled to at least two of the second rows of the second semiconductor patterns, and
wherein each of the second rows includes second semiconductor patterns arranged in the second direction.
15 . The semiconductor device of claim 13 , wherein the first semiconductor patterns and the second semiconductor patterns extend in a vertical direction crossing the first direction and the second direction.