3D memory semiconductor devices and structures with memory cells
A 3D memory device including: a first structure including a plurality of memory cells, where each memory cell of the plurality of memory cells includes at least one memory transistor, where each of the at least one memory transistor includes a source, a drain, and a channel, where the memory cell includes at least one charge trap structure, and where the at least one memory transistor is self-aligned to an overlaying another of the at least one memory transistor, both being processed following a same lithography step; and a control level including a memory controller circuit, where the control level includes a plurality of temperature sensors, where the control level is bonded to the first structure, and where the bonded includes hybrid bonding.
1 . A 3D memory device, the device comprising:
a first structure comprising a plurality of memory cells,
wherein each memory cell of said plurality of memory cells comprises at least one memory transistor,
wherein each of said at least one memory transistor comprises a source, a drain, and a channel,
wherein said memory cell comprises at least one charge trap structure, and
wherein said at least one memory transistor is self-aligned to an overlaying another said at least one memory transistor, both being processed following a same lithography step; and
a control level comprising a memory controller circuit,
wherein said control level comprises a plurality of temperature sensors,
wherein said memory controller circuit comprises a calibration mode control circuit,
wherein said control level is bonded to said first structure, and
wherein said bonded comprises hybrid bonding.
2 . The device according to claim 1 ,
wherein said channel comprises polysilicon,
wherein said source and/or said drain comprises metal atoms, and
wherein said metal atoms enable hot electron programming of said charge trap memory.
3 . The device according to claim 1 , further comprising:
a bottom level comprising a first crystallized silicon layer; and
a top level comprising a second crystallized silicon layer,
wherein said bottom level is overlaid by said first structure, and
wherein said first structure is overlaid by said top level.
4 . The device according to claim 1 ,
wherein said control level comprises a plurality of latch sense amplifiers.
5 . The device according to claim 1 ,
wherein at least one of said channel comprises recrystallized material.
6 . The device according to claim 1 ,
wherein said memory controller circuit comprises a row buffer.
7 . The device according to claim 1 ,
wherein said memory controller circuit comprises a configuration to perform a self-differential read cycle.
8 . A 3D memory device, the device comprising:
a first structure comprising a plurality of memory cells,
wherein each memory cell of said plurality of memory cells comprises at least one memory transistor,
wherein each of said at least one memory transistor comprises a source, a drain, and a channel;
a plurality of memory-line pillars,
wherein said plurality of memory-line pillars are vertically oriented, and
wherein said at least one memory transistor is self-aligned to an overlaying another said at least one memory transistor, both being processed following a same lithography step; and
a control level comprising a memory controller circuit,
wherein said memory controller circuit comprises a plurality of a row buffers,
wherein said memory controller circuit comprises a configuration to perform a differential read cycle,
wherein said control level is bonded to said first structure, and
wherein said bonded comprises hybrid bonding.
9 . The device according to claim 8 ,
wherein each of said at least one memory transistor is directly connected to at least one of said plurality of memory-line pillars.
10 . The device according to claim 8 ,
wherein at least one of said plurality of memory cells comprises a tunneling oxide thinner than 1 nm.
11 . The device according to claim 8 ,
wherein said plurality of memory cells comprise a partially or fully metalized source, and/or, a partially or fully metalized drain.
12 . The device according to claim 8 ,
wherein each memory cell of said plurality of memory cells comprises a charge trap memory,
wherein said channel comprises polysilicon,
wherein said channel is horizontally oriented,
wherein said source and/or said drain comprises metal atoms, and
wherein said metal atoms enable hot electron programming of said charge trap memory.
13 . The device according to claim 8 ,
wherein said control level comprises a plurality of temperature sensors.
14 . The device according to claim 8 ,
wherein said memory controller circuit comprises a calibration mode control circuit.
15 . A 3D memory device, the device comprising:
a first structure comprising a plurality of memory cells,
wherein each memory cell of said plurality of memory cells comprises at least one memory transistor,
wherein each of said at least one memory transistor comprises a source, a drain, and a channel;
a plurality of memory-line pillars,
wherein said plurality of memory-line pillars are vertically oriented, and
wherein said at least one memory transistor is self-aligned to an overlaying another said at least one memory transistor, both being processed following a same lithography step; and
a control level comprising a memory controller circuit,
a bottom level comprising a first crystallized silicon layer; and
a top level comprising a second crystallized silicon layer,
wherein said bottom level is overlaid by said first structure,
wherein said first structure is overlaid by said top level,
wherein said memory controller circuit comprises a calibration mode control circuit,
wherein said control level is bonded to said first structure, and
wherein said bonded comprises hybrid bonding.
16 . The device according to claim 15 ,
wherein said memory controller circuit comprises a row buffer.
17 . The device according to claim 15 ,
wherein said control level comprises a plurality of temperature sensors.
18 . The device according to claim 15 ,
wherein said memory controller circuit comprises a plurality of a row buffers.
19 . The device according to claim 15 ,
wherein said channel comprises recrystallized polysilicon.
20 . The device according to claim 15 ,
wherein said memory controller circuit comprises a configuration to perform a differential read cycle.