Semiconductor memory device, method for fabricating the same and electronic system including the same
There is provided a semiconductor memory device having improved reliability. The semiconductor memory device includes a cell substrate, a mold stack including mold insulating layers and gate electrodes, which are alternately stacked on the cell substrate, a semiconductor layer extended in a vertical direction crossing an upper surface of the cell substrate to pass through the mold stack, a blocking insulating pattern between the semiconductor layer and each of the gate electrodes, a charge storage layer including a charge trap portion between the semiconductor layer and the blocking insulating pattern and a first charge blocking portion between the semiconductor layer and each of the mold insulating layers, and a tunnel insulating layer between the semiconductor layer and the charge storage layer, wherein an oxygen concentration of the first charge blocking portion is higher than that of the charge trap portion.
1 . A semiconductor memory device comprising:
a cell substrate;
a mold stack including mold insulating layers and gate electrodes, which are alternately stacked on the cell substrate;
a semiconductor layer extended in a vertical direction crossing an upper surface of the cell substrate to pass through the mold stack;
a blocking insulating pattern between the semiconductor layer and each of the gate electrodes;
a charge storage layer including a charge trap portion and a first charge blocking portion, the charge trap portion between the semiconductor layer and the blocking insulating pattern, and the first charge blocking portion between the semiconductor layer and each of the mold insulating layers; and
a tunnel insulating layer between the semiconductor layer and the charge storage layer,
wherein an oxygen concentration of the first charge blocking portion is higher than that of the charge trap portion.
2 . The semiconductor memory device of claim 1 , wherein a thickness of the first charge blocking portion is greater than that of the charge trap portion.
3 . The semiconductor memory device of claim 1 , wherein
the charge trap portion includes a silicon nitride layer, and
the first charge blocking portion includes a silicon oxynitride layer.
4 . The semiconductor memory device of claim 1 , wherein
the blocking insulating pattern includes a convex surface that is convex toward the semiconductor layer, and
the charge trap portion is extended along the convex surface.
5 . The semiconductor memory device of claim 1 , wherein
each of the mold insulating layers includes a recess that is concave toward the semiconductor layer, and
the first charge blocking portion is extended along the recess.
6 . The semiconductor memory device of claim 1 , further comprising:
an isolation insulating pattern between the first charge blocking portion and the tunnel insulating layer.
7 . The semiconductor memory device of claim 1 , wherein
the charge storage layer further includes a second charge blocking portion between the charge trap portion and the first charge blocking portion, and
an oxygen concentration of the second charge blocking portion is higher than that of the first charge blocking portion.
8 . The semiconductor memory device of claim 7 , wherein a thickness of the second charge blocking portion is greater than that of the first charge blocking portion.
9 . The semiconductor memory device of claim 7 , wherein
the charge trap portion includes a silicon nitride layer,
the first charge blocking portion includes a silicon oxynitride layer, and
the second charge blocking portion includes a silicon oxide layer.
10 . The semiconductor memory device of claim 1 , further comprising:
a gate dielectric layer between the blocking insulating pattern and each of the gate electrodes.
11 . A semiconductor memory device comprising:
a cell substrate;
a mold stack including mold insulating layers and gate electrodes, which are alternately stacked on the cell substrate; and
a channel structure extended in a vertical direction crossing an upper surface of the cell substrate to pass through the mold stack,
wherein the channel structure includes:
a blocking insulating pattern on a side surface of each of the gate electrodes;
a charge storage layer including a charge trap portion extended along the blocking insulating pattern and a first charge blocking portion extended along a side surface of each of the mold insulating layers;
an isolation insulating pattern on the first charge blocking portion;
a tunnel insulating layer extended along the charge trap portion and the isolation insulating pattern; and
a semiconductor layer extended along the tunnel insulating layer,
wherein an oxygen concentration of the first charge blocking portion is higher than an oxygen concentration of the charge trap portion.
12 . The semiconductor memory device of claim 11 , wherein the blocking insulating pattern and the isolation insulating pattern are alternately arranged in the vertical direction.
13 . The semiconductor memory device of claim 11 , wherein each of the blocking insulating pattern and the isolation insulating pattern includes a silicon oxide layer.
14 . The semiconductor memory device of claim 11 , wherein
the isolation insulating pattern includes a concave surface that is concave toward the semiconductor layer, and
the tunnel insulating layer is extended along the concave surface.
15 . The semiconductor memory device of claim 11 , wherein
the charge storage layer further includes a second charge blocking portion between the charge trap portion and the first charge blocking portion, and
an oxygen concentration of the second charge blocking portion is higher than that of the first charge blocking portion.
16 . The semiconductor memory device of claim 15 , wherein
a thickness of the first charge blocking portion is greater than a thickness of the charge trap portion, and
a thickness of the second charge blocking portion is greater than a thickness of the first charge blocking portion.
17 . The semiconductor memory device of claim 15 , wherein
the charge trap portion includes a silicon nitride layer,
the first charge blocking portion includes a silicon oxynitride layer, and
the second charge blocking portion includes a silicon oxide layer.
18 . An electronic system comprising:
a main board;
a semiconductor memory device including a peripheral circuit structure and a memory cell structure, which are sequentially stacked on the main board; and
a controller electrically connected to the semiconductor memory device on the main board,
wherein the memory cell structure includes,
a cell substrate;
a mold stack including mold insulating layers and gate electrodes, which are alternately stacked on the cell substrate;
a semiconductor layer extended in a vertical direction crossing an upper surface of the cell substrate to pass through the mold stack;
a blocking insulating pattern between the semiconductor layer and each of the gate electrodes;
a charge storage layer including a charge trap portion and a first charge blocking portion, the charge trap portion between the semiconductor layer and the blocking insulating pattern, and the first charge blocking portion between the semiconductor layer and each of the mold insulating layers; and
a tunnel insulating layer between the semiconductor layer and the charge storage layer,
wherein an oxygen concentration of the first charge blocking portion is higher than an oxygen concentration of the charge trap portion.
19 . The electronic system of claim 18 , wherein
the charge storage layer further includes a second charge blocking portion between the charge trap portion and the first charge blocking portion, and
an oxygen concentration of the second charge blocking portion is higher than an oxygen concentration of the first charge blocking portion.
20 . The electronic system of claim 18 , wherein
the memory cell structure further includes:
a word line cutting region extended in a first horizontal direction crossing the vertical direction to cut the mold stack; and
a bit line extended in a second horizontal direction crossing the vertical direction and the first horizontal direction, and electrically connected to the semiconductor layer, and
the gate electrodes and the bit line are electrically connected to the controller.