Ferroelectric memory device with multi-level bit cell
A ferroelectric memory device includes a substrate including a source region and a drain region, and a gate structure disposed over the substrate. The gate structure includes a gate electrode including a plurality of electrode portions arranged in a first direction parallel to a top surface of the substrate, an oxide layer including a plurality of oxide portions corresponding respectively to the plurality of electrode portions, and a ferroelectric layer disposed between the gate electrode and the oxide layer along a second direction perpendicular to the first direction and including a plurality of ferroelectric portions corresponding respectively to the plurality of oxide portions. A least one of the plurality of oxide portions and at least one of the plurality of ferroelectric portions have different thicknesses along the second direction.
1 . A ferroelectric memory device, comprising:
a substrate including a channel region, a source region, and a drain region; and
a gate structure disposed over the substrate,
wherein the gate structure includes:
a gate electrode including a plurality of electrode portions arranged in a first direction parallel to a top surface of the substrate;
an oxide layer including a plurality of oxide portions corresponding respectively to the plurality of electrode portions, the plurality of oxide portions being disposed on and in direct contact with the channel region; and
a ferroelectric layer disposed between the gate electrode and the oxide layer along a second direction perpendicular to the first direction and including a plurality of ferroelectric portions corresponding respectively to the plurality of oxide portions, the plurality of ferroelectric portions being disposed in direct contact with each other,
wherein at least one of the plurality of oxide portions and at least one of the plurality of ferroelectric portions have different thicknesses along the second direction.
2 . The ferroelectric memory device of claim 1 , wherein:
the gate electrode includes a first electrode portion and a second electrode portion disposed over the substrate,
the oxide layer includes a first oxide portion and a second oxide portion, and
the ferroelectric layer includes a first ferroelectric portion and a second ferroelectric portion.
3 . The ferroelectric memory device of claim 2 , wherein the first electrode portion, the first oxide portion, the first ferroelectric portion are aligned along the second direction, and
each of the first electrode portion, the first oxide portion, the first ferroelectric portion has substantially the same length along the first direction.
4 . The ferroelectric memory device of claim 2 , wherein the first electrode portion and the second electrode portion have a first length and a second length, respectively, in the first direction, the first length being shorter than the second length.
5 . The ferroelectric memory device of claim 2 , wherein the first oxide portion has a first thickness, and the second oxide portion has a second thickness, the first thickness being lesser than the second thickness, and
wherein the first ferroelectric portion has a third thickness, and the second ferroelectric portion has a fourth thickness, the third thickness being greater than the fourth thickness.
6 . The ferroelectric memory device of claim 5 , wherein the second thickness is greater than that of the first thickness, and the third thickness is greater than that of the fourth thickness.
7 . The ferroelectric memory device of claim 2 , wherein the first oxide portion has a first thickness, and the second oxide portion has a second thickness, the second thickness being greater than the first thickness, and
wherein the first ferroelectric portion has a third thickness, and the second ferroelectric portion has a fourth thickness, the third thickness being substantially the same as the fourth thickness.
8 . The ferroelectric memory device of claim 2 , wherein the gate structure includes a first gate portion and a second gate portion, the first gate portion including the first electrode portion, the first ferroelectric portion, and the first oxide portion, the second gate portion including the second electrode portion, the second ferroelectric portion, and the second oxide portion,
wherein the ferroelectric memory device includes a first storage device including the first gate portion and a second storage device including the second gate portion, and
wherein the first and the second storage devices are part of the same ferroelectric field effect transistor (FeFET), each storage device being configured to store 1-bit data, so that the FeFET is configured to store 2-bit data.
9 . The ferroelectric memory device of claim 1 , wherein:
the gate electrode includes a first electrode portion, a second electrode portion, and a third electrode portion,
the oxide layer includes a first oxide portion, a second oxide portion, and a third oxide portion, at least two of the first to third oxide portions having different thicknesses, and
the ferroelectric layer includes a first ferroelectric portion, a second ferroelectric portion, and a third ferroelectric portion, at least two of the first to third ferroelectric portions having different thicknesses.
10 . The ferroelectric memory device of claim 9 , wherein the first oxide portion has a first thickness, the second oxide portion has a second thickness, and the third oxide portion has a third thickness, the second and the third thicknesses being substantially the same, the first thickness being lesser than each of the second the third thicknesses, and
wherein the first ferroelectric portion has a fourth thickness, the second ferroelectric portion has a fifth thickness, and the third ferroelectric portion has a sixth thickness, the fourth and the fifth thicknesses being substantially the same, the sixth thickness being greater than each of the fourth and the fifth thicknesses.
11 . The ferroelectric memory device of claim 10 , wherein each of the second and the third thicknesses is at least about twice that of the first thickness, and the sixth thickness is at least twice that of the fourth and the fifth thicknesses.
12 . The ferroelectric memory device of claim 9 , wherein the gate structure includes a first gate portion, a second gate portion, and a third gate portion, the first gate portion including the first electrode portion, the first ferroelectric portion, and the first oxide portion, the second gate portion including the second electrode portion, the second ferroelectric portion, and the second oxide portion, and the third gate portion including the third electrode portion, the third ferroelectric portion, and the third oxide portion,
wherein the ferroelectric memory device includes a first storage device including the first gate portion, a second storage device including the second gate portion, and a third storage device including the third gate portion, and
wherein the first, the second, and the third storage devices are part of the same ferroelectric field effect transistor (FeFET), each storage device being configured to store 1-bit data, so that the FeFET is configured to store 3-bit data.
13 . The ferroelectric memory device of claim 2 , further comprising:
a first well region disposed under the source region and the first ferroelectric portion;
a second well region disposed under the drain region and the second ferroelectric portion;
a first well contact to apply a first voltage to the first well region; and
a second well contact to apply a second voltage to the second well region,
wherein the first well region has a first conductive type and the second well region has a second conductive type different from the first conductive type.
14 . The ferroelectric memory device of claim 13 , wherein the first conductive type is N-type, and the second conductive type is P-type.
15 . A method of operating a ferroelectric memory device,
wherein the ferroelectric memory device comprises:
a substrate including a channel region, a source region, and a drain region; and
a gate structure disposed over the substrate,
wherein the gate structure includes:
a gate electrode including a plurality of electrode portions arranged in a first direction parallel to a top surface of the substrate;
an oxide layer including a plurality of oxide portions corresponding respectively to the plurality of electrode portions, the plurality of oxide portions being disposed on and in direct contact with the channel region; and
a ferroelectric layer disposed between the gate electrode and the oxide layer along a second direction perpendicular to the first direction and including a plurality of ferroelectric portions corresponding respectively to the plurality of oxide portions, the plurality of ferroelectric portions being disposed in direct contact with each other,
wherein at least one of the plurality of oxide portions and at least one of the plurality of ferroelectric portions have different thicknesses along the second direction, and
wherein the method comprises:
in order to write a first state, applying a supply voltage to the gate structure and applying a ground voltage to the drain region and the source region;
in order to write a second state, applying the supply voltage to the drain region and the source region and applying the ground voltage to the gate structure, and further applying a low voltage that is lower than the supply voltage to the gate structure and applying the ground voltage to the drain region and the source region;
in order to write a third state, applying the supply voltage to the gate structure and applying the ground voltage to the drain region and the source region, and further applying the low voltage to the drain region and the source region and applying the ground voltage to the gate structure; and
in order to write a fourth state, applying the supply voltage to the drain region and the source region and applying the ground voltage to the gate structure.
16 . The method of claim 15 , wherein the low voltage has a level corresponding to one of a half or a quarter of a level of the supply voltage.
17 . A memory device including a ferroelectric field effect transistor (FeFET), the FeFET comprising:
a substrate including a channel region, a source region, and a drain region; and
a gate structure disposed over the substrate,
wherein the gate structure includes:
an oxide layer disposed on and in direct contact with the channel region, the oxide layer including a first oxide portion and a second oxide portion;
a ferroelectric layer provided over the oxide layer, the ferroelectric layer including a first ferroelectric portion and a second ferroelectric portion that are disposed in direct contact with each other; and
a gate electrode provided over the ferroelectric layer, the gate electrode including a first gate portion and a second gate portion,
wherein the first gate portion, the first ferroelectric portion, and the first oxide portion define a first storage device that is configured to store 1-bit data,
wherein the second gate portion, the second ferroelectric portion, and the second oxide portion define a second storage device that is configured to store 1-bit data, and
wherein the FeFET includes a dielectric structure including the oxide layer and the ferroelectric layer, the dielectric structure being a step dielectric structure.
18 . The memory device of claim 17 , wherein the oxide layer has a step structure, or the ferroelectric layer has a step structure, or the oxide and the ferroelectric layers have the step structures.
19 . The memory device of claim 17 , wherein the dielectric structure has two or more steps.