Bipolar transistors

1 . A structure comprising:

a collector;

a base region above the collector;

an emitter laterally connecting to the base region;

an extrinsic base connecting to the base region; and

a gate electrode which includes a bottom surface in direct contact with a top surface of the base region.

2 . The structure of claim 1 , wherein the extrinsic base is laterally connecting to the base region, and the emitter is between a plurality of gate structures.

3 . The structure of claim 1 , further comprising a gate structure above the base region, the gate structure separating the extrinsic base from the emitter, both the extrinsic base and the emitter are partly below the gate structure, and the base region directly contacting a top semiconductor layer comprising silicon.

4 . The structure of claim 3 , wherein the gate structure is a same width as the base region.

5 . The structure of claim 3 , wherein the gate structure is a different width than the base region.

6 . The structure of claim 1 , wherein the emitter and the extrinsic base are epitaxial semiconductor material on a top semiconductor layer of semiconductor-on-insulator technology.

7 . The structure of claim 1 , wherein, from a top down perspective, the gate structure is “I” shaped.

8 . The structure of claim 7 , wherein the emitter is at a side of the gate structure and the extrinsic base is at an end of the gate structure.

9 . The structure of claim 1 , further comprising:

a second base region above the collector;

a first gate structure on the base region; and

a second gate structure on the second base region,

wherein the emitter is between the first gate structure and the second gate structure, and laterally connects to the base region and the second base region.

10 . The structure of claim 9 , wherein the extrinsic base region is located on opposing sides of the first gate structure and the second gate structure with respect to the emitter.

11 . A structure comprising:

a semiconductor region of a first conductivity type;

a sub-collector above the semiconductor region and comprising a second conductivity type;

a base region above the sub-collector, and further comprises the first conductivity type;

a gate structure above the base region;

an emitter on a first side of the gate structure; and

an extrinsic base on a second side of the gate structure,

wherein the emitter is on both sides of an “I” shape of the gate structure.

12 . The structure of claim 11 , wherein the emitter and the extrinsic base are separated from one another by the gate structure and are laterally connected to the base region, and the emitter is between a plurality of gate structures.

13 . The structure of claim 11 , wherein the base region comprises p-SiGe material, and the base region directly contacts a top semiconductor layer comprising silicon.

14 . The structure of claim 11 , wherein the base region is partially between a buried oxide layer.

15 . The structure of claim 14 , wherein the emitter and the extrinsic base comprise a semiconductor on insulator (SOI) substrate.

16 . The structure of claim 11 , wherein the extrinsic base is at ends of the gate structure.

17 . The structure of claim 11 , wherein the gate structure is a same width as the base region.

18 . The structure of claim 11 , wherein gate structure is a gate contacted structure forming a four terminal bipolar transistor.

19 . The structure of claim 11 , further comprising

a second base region above the collector; and

a second gate structure on the second base region;

wherein the emitter is between the gate structure and the second gate structure, and laterally connects to the base region and the second base region.

20 . A method comprising:

forming a collector;

forming a base region above the collector;

forming an emitter laterally connecting to the base region;

forming an extrinsic base connecting to the base region; and

forming a gate electrode which includes a bottom surface in direct contact with a top surface of the base region.