Semiconductor device comprising a transistor region and a capacitance adjusting region
A semiconductor device includes a capacitance adjusting region. The capacitance adjusting region includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, and a plurality of control trench gates. The first semiconductor layer is provided as a surface layer at an upper surface of the semiconductor substrate. The second semiconductor layer is selectively provided at an upper surface of the first semiconductor layer. The second semiconductor layer contacts a side surface of each of the control trench gates. The first semiconductor layer and the second semiconductor layer are electrically connected to an emitter electrode of a transistor. A control trench electrode of at least one control trench gate is electrically connected to a gate electrode of the transistor.
1 . A semiconductor device comprising:
a semiconductor substrate;
a transistor region provided in the semiconductor substrate and including a transistor; and
a capacitance adjusting region provided in the semiconductor substrate, the capacitance adjusting region including:
a first semiconductor layer of a first conductivity type provided as a surface layer at an upper surface of the semiconductor substrate in the capacitance adjusting region;
a second semiconductor layer of a second conductivity type as the surface layer of the semiconductor substrate in the capacitance adjusting region, the second semiconductor layer being selectively provided at an upper surface of the first semiconductor layer;
a drift layer of the second conductivity type in the capacitance adjusting region;
a collector layer of the first conductivity type in the capacitance adjusting region, the collector layer being provided below the drift layer; and
a plurality of control trench gates each including: a control trench insulating film formed on an inner wall of a control trench penetrating the second semiconductor layer from the upper surface of the semiconductor substrate, and having a tip located in the first semiconductor layer; and a control trench electrode formed inside the control trench across the control trench insulating film, wherein
the second semiconductor layer contacts a side surface of each of the control trench gates,
the first semiconductor layer and the second semiconductor layer are electrically connected to an emitter electrode of the transistor,
the control trench electrode of at least one control trench gate of the control trench gates is electrically connected to a gate electrode of the transistor.
2 . The semiconductor device according to claim 1 , wherein
the transistor region includes:
the drift layer of the second conductivity type provided between the upper surface and a lower surface of the semiconductor substrate in the transistor region;
a base layer of the first conductivity type provided over the drift layer;
a source layer of the second conductivity type as the surface layer at the upper surface of the semiconductor substrate in the transistor region, the source layer being selectively provided over the base layer;
a plurality of trench gates each including: a gate trench insulating film formed on an inner wall of a gate trench penetrating the source layer and the base layer from the upper surface of the semiconductor substrate, and having a tip located in the drift layer; and the gate electrode of the transistor formed inside the gate trench across the gate trench insulating film; and
the emitter electrode electrically connected to the source layer and insulated from the gate electrode of the transistor, wherein
the gate electrode of the transistor within at least one trench gate of the trench gates is electrically connected to the control trench electrode of the at least one control trench gate.
3 . The semiconductor device according to claim 2 , wherein
a pitch of the control trench gates is narrower than a pitch of the trench gates.
4 . The semiconductor device according to claim 2 , wherein
the control trench gates each have a depth from the upper surface of the semiconductor substrate greater than that of each of the trench gates from the upper surface of the semiconductor substrate.
5 . The semiconductor device according to claim 1 , further comprising:
a signal pad for detecting or controlling a state of the semiconductor substrate; and
a gate line electrically connecting the control trench electrode in the capacitance adjusting region and the gate electrode in the transistor region to each other, wherein
the emitter electrode extends from the transistor region into the capacitance adjusting region and is arranged between the signal pad and the gate line in a plan view,
the control trench gates extend in one direction at the upper surface of the semiconductor substrate while passing directly under the signal pad,
an end portion of each of the control trench gates is covered with the gate line,
the control trench electrode is electrically connected to the gate line only at the end portion of the at least one control trench gate, and
the first semiconductor layer is electrically connected to the emitter electrode only in a region between the signal pad and the gate line.
6 . The semiconductor device according to claim 5 , wherein
the control trench gates include a control trench gate not connected to the gate line, and
the control trench electrode of the control trench gate not connected to the gate line is electrically connected to the emitter electrode in the region between the signal pad and the gate line.
7 . The semiconductor device according to claim 2 , wherein
the control trench insulating film is thinner than the gate trench insulating film.
8 . The semiconductor device according to claim 5 , wherein
the control trench gates include a first control trench gate and a second control trench gate,
the gate line includes:
a first gate line pattern electrically connected to the control trench electrode of the first control trench gate at the end portion of the first control trench gate; and
a second gate line pattern electrically connected to the control trench electrode of the second control trench gate at the end portion of the second control trench gate, and
the second gate line pattern is disconnected.
9 . The semiconductor device according to claim 1 , wherein
the first semiconductor layer is the first conductivity type continuously from the upper surface of the semiconductor substrate to the tip of the control trench gates such that a concentration of dopants of the first conductivity type in the first semiconductor layer is greater than a concentration of dopants of the second conductivity type continuously from the upper surface of the semiconductor substrate to the tip of the control trench gates.
10 . The semiconductor device according to claim 1 , wherein
the transistor region includes:
the drift layer of the second conductivity type provided between the upper surface and a lower surface of the semiconductor substrate; and
a base layer of the first conductivity type provided over the drift layer, and
the first semiconductor layer is the first conductivity type continuously from the upper surface of the semiconductor substrate to the tip of the control trench gates such that a concentration of dopants of the first conductivity type in the first semiconductor layer is greater than a concentration of dopants of the second conductivity type continuously from the upper surface of the semiconductor substrate to the tip of the control trench gates.
11 . The semiconductor device according to claim 1 , wherein
the drift layer is spaced from a lower surface of the semiconductor substrate.