IP Library Granted Patent US 12684796
Granted Patent B2
US 12684796 · App. 17/965,803 · Granted Jul 14, 2026

High electron mobility transistor and method for forming the same

Inventor: Po-Yu Yang (Hsinchu City, TW)
Assignee: UNITED MICROELECTRONICS CORP.
H10D30/015H10D30/475H10D64/411
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Quick Facts
Patent No.
US 12684796
App. No.
17/965,803
Granted
Jul 14, 2026
Kind
B2
Abstract

A high electron mobility transistor (HEMT) includes a substrate, a channel layer on the substrate, a barrier layer on the channel layer, a gate structure on the barrier layer, a gate spacer on the gate structure, and a gate contact on the gate spacer. The gate contact includes a first portion and a second portion respectively at two sides of the gate spacer and directly contacting the gate structure.

Claims (18)

1 . A high electron mobility transistor, comprising:

a substrate;

a channel layer disposed on the substrate;

a barrier layer disposed on the channel layer;

a gate structure disposed on the barrier layer;

a gate spacer disposed on the gate structure, wherein the gate spacer is made of a dielectric material; and

a gate contact disposed on the gate spacer and comprising a first portion and a second portion respectively at two sides of the gate spacer and directly contacting the gate structure, wherein the gate structure comprises a first Schottky contact region being contacted by the first portion and a second Schottky contact region being contacted by the second portion.

2 . The high electron mobility transistor according to claim 1 , wherein the first portion comprises a first width, the second portion comprises a second width, the gate spacer comprises a spacer width, the gate structure comprises a gate width, wherein the first width and the second width are the same.

3 . The high electron mobility transistor according to claim 2 , wherein the first width, the second width, and the spacer width are the same.

4 . The high electron mobility transistor according to claim 2 , wherein a sum of the first width, the second width, and the spacer width is smaller than the gate width.

5 . The high electron mobility transistor according to claim 1 , wherein an outer sidewall of the first portion and an outer sidewall of the second portion are pulled back from a sidewall of the gate structure to the gate spacer by a distance, respectively.

6 . The high electron mobility transistor according to claim 1 , wherein the first Schottky contact region, the second Schottky contact region, and a top surface of the gate structure directly under the gate spacer are not coplanar.

7 . The high electron mobility transistor according to claim 1 , further comprising:

a passivation layer on the barrier layer and the gate structure, wherein the gate contact further comprises a connecting portion located on the gate spacer and the passivation layer and connecting between the first portion and the second portion; and

a source contact and a drain contact respectively at two sides of the gate structure, penetrating through the passivation layer and the barrier layer to contact the channel layer.

8 . The high electron mobility transistor according to claim 7 , wherein the first portion, the second portion, and the connecting portion are monolithic in structure.

9 . The high electron mobility transistor according to claim 7 , wherein the gate spacer and the passivation layer comprise a same dielectric material.

10 . The high electron mobility transistor according to claim 1 , wherein in a plane view, the first portion, the second portion, and the gate structure extend along a same direction.