Vertical field effect transistor including channel having GaN and AIGaN regions

1 . A vertical field effect transistor, comprising:

a trench structure having a first side and a second side opposite the first side, a field effect transistor (FET) channel including a gallium nitride (GaN) region and an aluminum gallium nitride (AlGaN) region adjacent to the GaN region, and the GaN region includes a p-conductive first region and a second region formed on the p-conductive first region; and

a source electrode that is electroconductively connected to the p-conductive first region of the GaN region and to the AlGaN region.

2 . The vertical field effect transistor as recited in claim 1 , wherein the second region of the GaN region is n-conductive or intrinsically conductive.

3 . The vertical field effect transistor as recited in claim 1 , further comprising:

a GaN substrate having a first side and a second side opposite the first side, the trench structure being situated at the first side of the GaN substrate, and a drain electrode being situated at the second side of the GaN substrate.

4 . The vertical field effect transistor as recited in claim 3 , further comprising:

a second trench structure adjacent to the trench structure, the p-conductive region of the GaN region extending to below a base of the second trench structure, where it contacts the source electrode.

5 . The vertical field effect transistor as recited in claim 3 , wherein the first and second sides of the trench structure each encompass an angle with the GaN substrate in a range of greater than 0° and less than 90°.

6 . The vertical field effect transistor as recited in claim 5 , wherein the angle of the first side of the trench structure differs from the angle of the second side of the trench structure.

7 . The vertical field effect transistor as recited in claim 1 , further comprising:

a gate dielectric that is formed on the AlGaN region, and a gate electrode that is formed on the gate dielectric.

8 . The vertical field effect transistor as recited in claim 1 , further comprising a GaN substrate, wherein the trench structure is above the GaN substrate.

9 . The vertical field effect transistor as recited in claim 8 , wherein the first and second sides of the trench structure each encompasses an angle with the GaN substrate in a range of greater than 0° and less than 90°.

10 . The vertical field effect transistor as recited in claim 8 , further comprising:

a gate dielectric on the AlGaN region;

a gate electrode on the gate dielectric; and

a drain electrode that is at a side of the GaN substrate that is opposite from the side with the trench structure.

11 . A method for manufacturing a vertical field effect transistor, the method comprising the following steps:

forming a trench structure on or above a gallium nitride (GaN) substrate, the trench structure having a first side and a second side opposite the first side, a field effect transistor (FET) channel including a GaN region and an aluminum gallium nitride (AlGaN) region adjacent to the GaN region, and the GaN region including a p-conductive first region and a second region formed on the p-conductive first region; and

forming a source electrode that is electroconductively connected to the p-conductive first region of the GaN region and to the AlGaN region.

12 . The method as recited in claim 11 , wherein the first and second sides of the trench structure each encompass an angle with the GaN substrate in a range of greater than 0° and less than 90°.

13 . The method as recited in claim 11 , further comprising:

forming a gate dielectric on the AlGaN region and a gate electrode on the gate dielectric; and

forming a drain electrode at one side of the GaN substrate that is opposite from the side with the trench structure.