Thin-sheet FinFET device

1 . A semiconductor device, comprising:

a fin protruding upwardly from a substrate, the fin including a first sidewall and an opposing second sidewall and a top surface extending between the first and second sidewalls;

a two-dimensional material layer disposed on the first and second sidewalls of the fin without being disposed on the top surface of the fin, wherein the two-dimensional material layer includes a flat portion extending laterally away from the fin, wherein the two-dimensional material layer includes a transition metal dichalcogenide; and

a gate stack disposed on the fin, the gate stack contacting a channel region defined in the two-dimensional material layer.

2 . The semiconductor device of claim 1 , further comprising:

a dielectric isolation structure disposed on the substrate, wherein the flat portion of the two-dimensional material layer has a bottom surface directly facing a top surface of the dielectric isolation structure.

3 . The semiconductor device of claim 2 , wherein a portion of the gate stack is disposed on the dielectric isolation structure, and the portion of the gate stack has a bottom surface directly facing the top surface of the dielectric isolation structure.

4 . The semiconductor device of claim 3 , further comprising:

a gate contact plug landing on the portion of the gate stack, wherein the gate contact plug is directly above the dielectric isolation structure.

5 . The semiconductor device of claim 1 , wherein a first source/drain feature is defined in the two-dimensional material layer on a first side of the channel region and a second source/drain feature is defined in the two-dimensional material layer on a second side of the channel region, the second side of the channel region being opposite the first side.

6 . The semiconductor device of claim 1 , wherein the gate stack includes a gate dielectric layer in contact with the top surface of the fin.

7 . The semiconductor device of claim 1 , wherein the two-dimensional material layer is a monolayer.

8 . The semiconductor device of claim 1 , wherein the fin includes a base portion and a top portion, and wherein the base portion and the top portion of the fin include different material compositions.

9 . The semiconductor device of claim 8 , wherein the base portion of the fin and the substrate include a same semiconductor material, and wherein the top portion of the fin includes a dielectric material.

10 . A semiconductor device, comprising:

a substrate;

a dielectric isolation structure disposed on the substrate;

a fin protruding through the dielectric isolation structure, wherein above a top surface of the dielectric isolation structure the fin includes a first sidewall and an opposing second sidewall and a top surface of the fin extending between the first and second sidewalls;

a two-dimensional material layer, wherein in a cross-sectional view of the semiconductor device the two-dimensional material layer includes a first portion disposed on the first and second sidewalls of the fin and a second portion disposed on the top surface of the dielectric isolation structure, wherein in the cross-sectional view of the semiconductor device a portion of the top surface of the fin is free of direct contact with the two-dimensional material layer, and wherein the two-dimensional material layer includes a transition metal dichalcogenide; and

a gate stack disposed on a channel region defined in the two-dimensional material layer.

11 . The semiconductor device of claim 10 , further comprising:

a source/drain contact plug in electric coupling with a source/drain region defined in the two-dimensional material layer.

12 . The semiconductor device of claim 11 , wherein the source/drain contact plug is directly above the top surface of the fin.

13 . The semiconductor device of claim 11 , wherein the source/drain contact plug is directly above the top surface of the dielectric isolation structure.

14 . The semiconductor device of claim 10 , wherein a portion of the gate stack is in direct contact with the dielectric isolation structure.

15 . The semiconductor device of claim 10 , further comprising:

a gate contact plug in electrical coupling with the gate stack, wherein a bottom portion of the gate contact plug is below the top surface of the fin.

16 . A semiconductor device, comprising:

a rib structure disposed on a substrate, the rib structure including a first sidewall and an opposing second sidewall and a top surface extending between the first and second sidewalls;

a two-dimensional material layer disposed directly on the first and second sidewalls of the rib structure, wherein a first channel region and a first source/drain region are defined in the two-dimensional material layer disposed directly on the first sidewall and a second channel region and a second source/drain region are defined in the two-dimensional material layer disposed directly on the second sidewall, wherein the first and second channel regions are spaced apart, wherein the first and second source/drain regions are spaced apart, wherein the two-dimensional material layer includes a transition metal dichalcogenide; and

a gate stack disposed on the rib structure, the gate stack including a gate dielectric layer and a gate electrode layer, the gate dielectric layer physically contacting the first and second channel regions of the two-dimensional material layer.

17 . The semiconductor device of claim 16 , further comprising:

a conductive feature electrically coupling the first and second source/drain regions.

18 . The semiconductor device of claim 17 , further comprising:

a source/drain contact plug landing on the conductive feature, wherein the source/drain contact plug is directly above the top surface of the rib structure.

19 . The semiconductor device of claim 16 , wherein the top surface of the rib structure is substantially free of physical contact with the two-dimensional material layer.

20 . The semiconductor device of claim 16 , wherein the gate dielectric layer physically contacts the two-dimensional material layer.