Semiconductor device including a trench gate type MOSFET and method of manufacturing the same
Disclosed is a technique for improving performance of a semiconductor device having a trench gate type power MOSFET. Concretely, a method of manufacturing a semiconductor device having a trench gate type power MOSFET comprising: forming a trench in a semiconductor substrate; introducing both of a p-type impurity (Boron) and carbon (C) into a bottom surface of the trench to form a p-type impurity introduced region; forming a gate electrode to fill the trench; forming a channel forming region and a source region at the side of the trench in which the gate electrode is filled; and subjecting a heat treatment to the p-type impurity introduced region to form an electric field relaxation layer having suppressed crystal defects and a controlled shape.
1 . A method of manufacturing a semiconductor device, the method comprising:
(a) preparing a semiconductor substrate of a first conductivity type;
(b) forming a plurality of grooves on a main surface of the semiconductor substrate;
(c) introducing a first impurity of a second conductivity type and carbon into a bottom surface of the plurality of grooves by ion implantation with an implantation angle of 0 degrees, thereby forming a first semiconductor region of the second conductivity type different from the first conductivity type in the semiconductor substrate under the bottom surface of the plurality of grooves;
(d) introducing a second impurity of the second conductivity type and carbon into a side surface of the plurality of grooves by oblique ion implantation, thereby forming a third semiconductor region of the second conductivity type in the semiconductor substrate at the side surface of the plurality of grooves;
(e) after the (c) and (d), forming a gate electrode inside the plurality of grooves via a first insulating film;
(f) after the (e), forming a second semiconductor region of the second conductivity type in the semiconductor substrate at a side surface of the plurality of grooves between the adjacent grooves, the second semiconductor region being used as a channel forming region; and
(g) forming a source region of the first conductivity type in the semiconductor substrate from a main surface of the semiconductor substrate to the second semiconductor region,
wherein a bottom of the semiconductor substrate is used as a drain region of the first conductivity type, and
wherein the source region, the drain region, the gate electrode, and the first semiconductor region comprise a field effect transistor.
2 . The method according to claim 1 , wherein the (f) includes:
(f1) introducing impurities of the second conductivity type into the semiconductor substrate in contact with a side surface of the grooves, and
(f2) after the (f1), forming the second semiconductor regions by performing a heat treatment to diffuse the impurities of the second conductivity type.
3 . The method according to claim 1 , wherein the first semiconductor region is formed by implanting the impurity of the second conductivity type and the carbon into the same region of the semiconductor substrate by ion implantations in the (c).
4 . The method according to claim 1 , further comprising a (e1) forming a first electrode in the plurality of grooves via a second insulating film prior to the formation of the gate electrode, wherein the (e) includes forming the gate electrode over the first electrode.