Metal oxide semiconductor field effect transistor and method of manufacturing
A Metal Oxide Semiconductor (MOS), Field Effect Transistor (FET), (MOSFET) is provided, including a semiconductor body having a first major surface, and two trenches extending in the semiconductor body from the first major surface, a source region of a first conductivity type adjacent sidewalls of the two trenches at the first major surface, a drain region of the first conductivity type adjacent the two trenches at a position distant from the source region, a channel-accommodating region, of a second conductivity type opposite to the first conductivity type, adjacent the sidewalls of the two trenches between the source region and the drain region, and a first of the two trenches extends further into the semiconductor body compared to a second of the two trenches.
1 . A Metal Oxide Semiconductor Field Effect Transistor (MOSFET), comprising:
a semiconductor body having a first major surface, and two trenches extending in the semiconductor body from the first major surface;
a source region of a first conductivity type adjacent to sidewalls of the two trenches at the first major surface;
a drain region of the first conductivity type adjacent to the two trenches at a position distant from the source region;
a channel-accommodating region of a second conductivity type opposite to the first conductivity type, adjacent to the sidewalls of the two trenches between the source region and the drain region;
wherein of the two trenches, a first trench extends further into the semiconductor body compared to a second trench of the two trenches, and
wherein the drain region has a doping profile that is monotonically decreasing from a point B in a direction away from the channel-accommodating region, and wherein at point B a mesa width is the smallest.
2 . The MOSFET in accordance with claim 1 , wherein the first trench of the two trenches has a non-uniform dielectric thickness.
3 . The MOSFET in accordance with claim 2 , wherein:
the first trench of the two trenches is provided with an oxide layer,
and wherein the oxide layer has a thickness that is non-uniform in a direction in which the first trench extends in the semiconductor body.
4 . The MOSFET in accordance with claim 2 , wherein the first trench of the two trenches has a drop-shaped cross-section.
5 . The MOSFET in accordance with claim 2 , wherein the first of the two trenches extends 3 to 5 times further into the semiconductor body compared to the second of the two trenches.
6 . The MOSFET in accordance with previous claim 2 , wherein the first of the two trenches has a profile so that a smallest mesa width is about 0.3-0.6 times a largest mesa width.
7 . The MOSFET in accordance with claim 1 , wherein the first trench of the two trenches is provided with an oxide layer, and wherein the oxide layer has a thickness that is non-uniform in a direction in which the first trench extends in the semiconductor body.
8 . The MOSFET in accordance with claim 1 , wherein the first trench of the two trenches has a drop-shaped cross-section.
9 . The MOSFET in accordance with claim 1 , wherein the first of the two trenches extends 2 to 6 times further into the semiconductor body compared to the second of the two trenches.
10 . The MOSFET in accordance with claim 1 , wherein the first of the two trenches has a profile so that a smallest mesa width is about 0.3 to 0.6 times a largest mesa width.
11 . The MOSFET in accordance with claim 1 , wherein the first of the two trenches is connected to a source terminal of the MOSFET, and wherein the second of the two trenches is connected to a gate terminal of the MOSFET.
12 . The MOSFET in accordance with claim 1 , wherein the channel-accommodating region is isolated from the sidewalls of the two trenches by oxide layers, respectively.
13 . The MOSFET in accordance with claim 12 , wherein the oxide layers have a thickness at the channel-accommodating region, that is in a range from 32 nm to 70 nm.
14 . The MOSFET in accordance with claim 12 , wherein the oxide layers have a thickness at the channel-accommodating region, that is in a range from 5 nm to 25 nm.
15 . The MOSFET in accordance with claim 1 , wherein:
the first of the two trenches has a profile so that a smallest mesa width is about 0.3 to 0.6 times a largest mesa width;
wherein the drain region has a doping profile that is monotonically decreasing from a point B in a direction away from the channel-accommodating region, and wherein at point B a mesa width is the smallest; and
wherein the first trench of the two trenches has a drop-shaped cross-section.
16 . A method of manufacturing a Metal Oxide Semiconductor Field Effect Transistor (MOSFET), in accordance with claim 1 , wherein the method comprises the steps of:
providing a semiconductor substrate; and
creating the first and second trench in the semiconductor substrate.
17 . The method of manufacturing a MOSFET in accordance with claim 16 , wherein the method comprises the steps of:
creating the first trench in the semiconductor substrate and, when completed, creating the second trench in the semiconductor substrate.
18 . A Metal Oxide Semiconductor Field Effect Transistor (MOSFET), comprising:
a semiconductor body having a first major surface, and two trenches extending in the semiconductor body from the first major surface;
a source region of a first conductivity type adjacent to sidewalls of the two trenches at the first major surface;
a drain region of the first conductivity type adjacent to the two trenches at a position distant from the source region;
a channel-accommodating region of a second conductivity type opposite to the first conductivity type, adjacent to the sidewalls of the two trenches between the source region and the drain region; and
wherein of the two trenches, a first trench extends further into the semiconductor body compared to a second trench of the two trenches, and,
wherein both the first and the second of the two trenches are connected to a gate terminal of the MOSFET.
19 . A Metal Oxide Semiconductor Field Effect Transistor (MOSFET), comprising:
a semiconductor body having a first major surface, and two trenches extending in the semiconductor body from the first major surface;
a source region of a first conductivity type adjacent to sidewalls of the two trenches at the first major surface;
a drain region of the first conductivity type adjacent to the two trenches at a position distant from the source region;
a channel-accommodating region, of a second conductivity type opposite to the first conductivity type, adjacent to the sidewalls of the two trenches between the source region and the drain region; and
wherein of the two trenches, a first trench extends further into the semiconductor body compared to a second trench of the two trenches;
wherein the first of the two trenches has a profile so that a smallest mesa width is about 0.3 to 0.6 times a largest mesa width;
wherein the drain region has a doping profile that is monotonically decreasing from a point B in a direction away from the channel-accommodating region, and wherein at point B a mesa width is the smallest; and
wherein the first trench of the two trenches has a drop-shaped cross-section.