Methods for fabricating semiconductor device having nanostructure transistor with cap layer

1 . A method for forming a semiconductor device structure, comprising:

forming a stack of semiconductor layers over a substrate, the stack of the semiconductor layers comprising a plurality of first semiconductor layers and a plurality of second semiconductor layers alternatingly stacked;

forming a fin structure from the stack of the semiconductor layers and the substrate;

forming a sacrificial gate structure over a portion of the fin structure;

removing portions of the fin structure not covered by the sacrificial gate structure to expose a portion of the substrate;

removing edge portions of the second semiconductor layers to form cavities between adjacent first semiconductor layers;

forming a cap layer on exposed surfaces of each of the first and second semiconductor layers, wherein the cap layer is formed of a semiconductor material;

forming a dielectric spacer on the cap layer and filling in the cavities;

after forming the dielectric spacer, forming a facetted structure on entire exposed surfaces of the cap layer;

forming a source/drain feature on opposite sides of the sacrificial gate structure, the source/drain feature being in contact with the dielectric spacer and the facetted structure;

removing the sacrificial gate structure and the plurality of second semiconductor layers to expose portions of the plurality of first semiconductor layers and the cap layer; and

forming a gate electrode layer to surround the exposed portion of at least one of the plurality of first semiconductor layers, wherein the gate electrode layer is separated from the dielectric spacer by the cap layer.

2 . The method of claim 1 , further comprising:

after forming a cap layer on entire exposed surfaces of each of the first and second semiconductor layers, selectively removing the cap layer from the exposed surfaces of the first semiconductor layers in an N-type region while keeping the cap layer on the exposed surfaces of the first semiconductor layers in a P-type region.

3 . The method of claim 1 , wherein the cap layer is a boron-doped silicon.

4 . A method for forming a semiconductor device structure, comprising:

forming a sacrificial gate structure over a portion of a fin structure, the fin structure comprising a plurality of first semiconductor layers and a plurality of second semiconductor layers alternatingly stacked;

removing portions of the fin structure not covered by the sacrificial gate structure;

removing edge portions of the second semiconductor layers to form cavities between adjacent first semiconductor layers;

forming a cap layer on exposed surfaces of the sacrificial gate structure and each of the first and second semiconductor layers;

forming a dielectric spacer on the cap layer and filling in the cavities;

after forming the dielectric spacer, removing the cap layer on exposed surfaces of the sacrificial gate structure;

after removing the cap layer on exposed surfaces of the sacrificial gate structure, forming a facetted structure on entire surface of the cap layer; and

forming a source/drain feature on opposite sides of the sacrificial gate structure, the source/drain feature being in contact with the facetted structure and the dielectric spacer.

5 . The method of claim 4 , further comprising:

removing the sacrificial gate structure and the plurality of second semiconductor layers to expose portions of the plurality of first semiconductor layers and the cap layer; and

forming a gate electrode layer to surround the exposed portion of at least one of the plurality of first semiconductor layers.

6 . The method of claim 4 , wherein the facetted structure is formed on the entire exposed surfaces of the cap layer.

7 . The method of claim 4 , wherein the cap layer is formed of a doped semiconductor.

8 . The method of claim 7 , wherein the cap layer is a boron-doped silicon.

9 . The method of claim 4 , wherein the cap layer is formed of an oxide-based dielectric, nitride-based dielectric, carbon-based dielectric, or a high-K dielectric.

10 . The method of claim 4 , further comprising:

after removing the cap layer on exposed surfaces of the sacrificial gate structure, selectively removing the cap layer from the exposed surfaces of the first semiconductor layers in an N-type region while keeping the cap layer on the exposed surfaces of the first semiconductor layers in a P-type region.

11 . A method for forming a semiconductor device structure, comprising:

forming a sacrificial gate structure over a portion of a fin structure, the fin structure comprising a plurality of first semiconductor layers and a plurality of second semiconductor layers alternatingly stacked;

removing portions of the fin structure not covered by the sacrificial gate structure;

removing edge portions of the second semiconductor layers to form cavities between adjacent first semiconductor layers;

forming a cap layer on exposed surfaces of the sacrificial gate structure and each of the first and second semiconductor layers, wherein the cap layer is formed of a doped semiconductor;

forming a dielectric spacer on the cap layer and filling in the cavities, wherein the dielectric spacer is formed of a material chemically different than the doped semiconductor;

after forming the dielectric spacer, removing the cap layer on the exposed surfaces of the sacrificial gate structure;

forming a facetted structure on exposed surfaces of the cap layer; and

forming a source/drain feature on opposite sides of the sacrificial gate structure, the source/drain feature being in contact with the facetted structure and the dielectric spacer.

12 . The method of claim 11 , wherein the doped semiconductor is boron-doped silicon.

13 . The method of claim 12 , wherein the boron concentration is in a range from about zero to about 3E21 cm −3 .

14 . The method of claim 11 , further comprising:

after removing the cap layer on the exposed surfaces of the sacrificial gate structure and the first semiconductor layers, removing a portion of the cap layer between the first semiconductor layers.

15 . The method of claim 14 , wherein a portion of the source/drain feature is disposed between and in contact with dielectric spacer and a portion of the first semiconductor layer.

16 . The method of claim 11 , further comprising:

after forming the source/drain feature, removing the sacrificial gate structure and the plurality of second semiconductor layers to expose portions of the plurality of first semiconductor layers and the cap layer; and

forming a gate electrode layer to surround the exposed portion of at least one of the plurality of first semiconductor layers.

17 . The method of claim 16 , further comprising:

prior to forming the gate electrode layer, removing the exposed portions of the cap layer.