Reduced gate top CD with wrap-around gate contact
A semiconductor structure is presented including a plurality of field effect transistor (FET) devices, each FET device having a different gate threshold voltage, first spacers disposed on sidewalls of each FET device, second spacers disposed over and in direct contact with the first spacers, the second spacers having a width greater than a width of the first spacers, and a gate contact directly contacting an FET device of the plurality of FET devices, where only an upper portion of the gate contact directly contacts third spacers on opposed ends thereof. The second spacers can have a bi-layer configuration and the gate contact wraps around a top portion of the FET device in direct contact with the gate contact.
1 . A semiconductor structure comprising:
a plurality of field effect transistor (FET) devices, each of the plurality of FET devices having a different gate threshold voltage;
first spacers disposed on opposed ends of each of the plurality of FET devices;
second spacers disposed over and in direct contact with the first spacers, the second spacers having a width greater than a width of the first spacers;
third spacers disposed in an interlayer dielectric; and
a gate contact directly contacting one of the plurality of FET devices, wherein only an upper portion of the gate contact directly contacts third spacers on opposed ends of the upper portion of the gate contact.
2 . The semiconductor structure of claim 1 , wherein the one of the plurality of FET devices directly contacting the gate contact includes a first work function metal (WFM) layer, a second WFM layer, and a third WFM layer.
3 . The semiconductor structure of claim 2 , wherein the first WFM layer directly contacts sidewalls of the first spacers and the second WFM layer directly contacts sidewalls of the second spacers.
4 . The semiconductor structure of claim 2 , wherein the third WFM layer rests within the second WFM layer.
5 . The semiconductor structure of claim 2 , wherein the third WFM layer directly contacts a bottom surface of the gate contact.
6 . The semiconductor structure of claim 1 , wherein the third spacers are vertically aligned with the first spacers and the second spacers.
7 . The semiconductor structure of claim 1 , wherein the second spacers directly contact an upper portion of the one of the plurality of FET devices that is directly contacting the gate contact.
8 . A method comprising:
constructing a plurality of field effect transistor (PET) devices, each of the plurality of FET devices having a different gate threshold voltage;
forming first spacers on opposed ends of each of the plurality of FET devices;
forming second spacers over and in direct contact with the first spacers, the second spacers having a width greater than a width of the first spacers;
forming third spacers in an opening of an interlayer dielectric; and
disposing a gate contact in direct contact with one of the plurality of FET devices, wherein only an upper portion of the gate contact directly contacts third spacers on opposed ends the upper portion of the gate contact.
9 . The method of claim 8 , wherein the second spacers have a bi-layer configuration.
10 . The method of claim 8 , wherein the gate contact wraps around a top portion of the one of the plurality of FET devices in direct contact with the gate contact.