IP Library Granted Patent US 12684817
Granted Patent B2
US 12684817 · App. 18/054,958 · Granted Jul 14, 2026

Spacer cut for asymmetric source/drain epitaxial structure in stacked FET

Inventors: Su Chen Fan (Cohoes, NY); Albert M. Young (Fishkill, NY); Ruilong Xie (Niskayuna, NY); Prabudhya Roy Chowdhury (Albany, NY); Jay William Strane (Warwick, NY)
Assignee: International Business Machines Corporation
H10D30/6735H10D30/6757H10D62/121H10D64/017H10D84/8312H10D84/856
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Quick Facts
Patent No.
US 12684817
App. No.
18/054,958
Granted
Jul 14, 2026
Kind
B2
Abstract

Embodiments of the invention include a stacked device having a first epitaxial region and a second epitaxial region vertically displaced from the first epitaxial region. The first epitaxial region comprising an asymmetric profile with a horizontal protrusion. A contact is formed on the horizontal protrusion of the first epitaxial region

Claims (23)

1 . A semiconductor structure comprising:

a first epitaxial region and a second epitaxial region vertically displaced from the first epitaxial region, the first epitaxial region comprising an asymmetric profile with a horizontal protrusion, wherein a spacer material confines one side of the first epitaxial region and is formed on a portion of a shallow trench isolation (STI) region, an entirety of a top surface of the first epitaxial region being free of the spacer material; and

a contact formed on the horizontal protrusion of the first epitaxial region, wherein the horizontal protrusion is opposite the one side and free of confinement by the spacer material, wherein an interlayer dielectric material abuts the top surface of the first epitaxial region, wherein the horizontal protrusion extends beyond an edge of the second epitaxial region.

2 . The semiconductor structure of claim 1 , wherein a stack comprises the first epitaxial region and the second epitaxial region.

3 . The semiconductor structure of claim 1 , wherein a first transistor comprises the first epitaxial region and a second transistor comprises the second epitaxial region, the first and second transistors being vertically stacked.

4 . The semiconductor structure of claim 1 , wherein one side of the first epitaxial region is flat and is opposite the horizontal protrusion.

5 . The semiconductor structure of claim 1 , wherein the second epitaxial region comprises a symmetric profile.

6 . The semiconductor structure of claim 1 , wherein the contact formed on the horizontal protrusion of the first epitaxial region is physically and laterally separated from another contact formed on the second epitaxial region.

7 . The semiconductor structure of claim 1 , wherein the first epitaxial region is below the second epitaxial region.

8 . The semiconductor structure of claim 1 , wherein the first epitaxial region is epitaxially grown with the horizontal protrusion.

9 . The semiconductor structure of claim 1 , wherein the one side extends from a top to a bottom of the first epitaxial region such that the spacer material is contact with the first epitaxial region from the top to the bottom, thereby preventing the first epitaxial region from extending beyond the spacer material.

10 . The semiconductor structure of claim 1 , wherein the spacer material confining the one side of the first epitaxial region is in contact with the STI region.

11 . The semiconductor structure of claim 1 , wherein the spacer material is a dielectric material.

12 . A method comprising:

providing a first epitaxial region and a second epitaxial region vertically displaced from the first epitaxial region, the first epitaxial region comprising an asymmetric profile with a horizontal protrusion, wherein a spacer material confines one side of the first epitaxial region and is formed on a portion of a shallow trench isolation (STI) region, an entirety of a top surface of the first epitaxial region being free of the spacer material; and

forming a contact on the horizontal protrusion of the first epitaxial region, wherein the horizontal protrusion is opposite the one side and free of confinement by the spacer material, wherein an interlayer dielectric material abuts the top surface of the first epitaxial region, wherein the horizontal protrusion extends beyond an edge of the second epitaxial region.

13 . The method of claim 12 , wherein a stack comprises the first epitaxial region and the second epitaxial region.

14 . The method of claim 12 , wherein a first transistor comprises the first epitaxial region and a second transistor comprises the second epitaxial region, the first and second transistors being vertically stacked.

15 . The method of claim 12 , wherein one side of the first epitaxial region is flat and is opposite the horizontal protrusion.

16 . The method of claim 12 , wherein the second epitaxial region comprises a symmetric profile.

17 . The method of claim 12 , wherein the contact formed on the horizontal protrusion of the first epitaxial region is physically and laterally separated from another contact formed on the second epitaxial region.

18 . The method of claim 12 , wherein the first epitaxial region is below the second epitaxial region.

19 . The method of claim 12 , wherein the first epitaxial region is epitaxially grown with the horizontal protrusion.