IP Library Granted Patent US 12684823
Granted Patent B2
US 12684823 · App. 17/831,950 · Granted Jul 14, 2026

Layer structures including configuration increasing operation characteristics, methods of manufacturing the same, electronic devices including layer structures, and electronic apparatuses including electronic devices

Inventors: Minsu Seol (Seoul, KR); Junyoung Kwon (Seoul, KR); Minseok Yoo (Suwon-si, KR)
Assignee: Samsung Electronics Co., Ltd.
H10D30/791H10D30/031H10D30/6735H10D30/6739H10D30/6757H10D30/751H10D30/792H10D30/794H10D62/121H10D62/881H10D62/882H10D62/883H10D84/0167H10D84/038
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Quick Facts
Patent No.
US 12684823
App. No.
17/831,950
Granted
Jul 14, 2026
Kind
B2
Abstract

Provided are a layer structure including a configuration capable of increasing the operation characteristics of a device including the layer structure, a method of manufacturing the layer structure, an electronic device including the layer structure, and an electronic apparatus including the electronic device. The layer structure includes a first layer and a second layer on one surface of the first layer and facing the first layer. The first layer and the second layer overlap each other. One layer of the first layer and the second layer has a trace of applied strain, and an other layer of the first layer and the second layer is a strain-inducing layer that applies a strain to the one layer.

Claims (25)

1 . An electronic device comprising:

a substrate;

a first electrode on the substrate;

a second electrode on the substrate and separated from the first electrode;

a gate electrode on the substrate and separated from the first electrode and the second electrode;

a channel layer connected to the first electrode and the second electrode, the channel layer separated from the gate electrode; and

a stressor layer on the channel layer is a strain-inducing layer,

wherein the channel layer has a trace of applied strain,

wherein the channel layer comprises a two-dimensional material,

wherein a thickness of the stressor layer is greater than a thickness of the channel layer, and

wherein the channel layer, the gate electrode, and the stressor layer vertically overlap each other.

2 . The electronic device of claim 1 , further comprising:

a buffer layer between the channel layer and the stressor layer.

3 . The electronic device of claim 1 ,

wherein the channel layer includes a plurality of channels, and

the plurality of channels are vertically stacked and have a hollow closed-type cross-sectional structure.

4 . The electronic device of claim 1 ,

wherein the channel layer includes a plurality of horizontal parts and a plurality of vertical parts,

the plurality of horizontal parts are sequentially stacked on the substrate, and

the plurality of vertical parts contact the first electrode and the second electrode.

5 . The electronic device of claim 1 ,

wherein the two-dimensional material comprises transition metal dichalcogenide (TMD), black phosphorus (BP), or a material including carbon (C).

6 . The electronic device of claim 5 , wherein the TMD comprises MoS 2 , WS 2 , MoSe 2 , or WSe 2 .

7 . The electronic device of claim 1 ,

the stressor layer surrounds the channel layer.