Field effect transistor
View Patent ↗In a field effect transistor, trench lower layers are disposed directly below corresponding trenches. Deep layers of p-type extend along a first direction intersecting the trenches and are arranged at intervals along a second direction orthogonal to the first direction. A drain-side layer of n-type is distributed from a position in contact with a lower surface of a body layer to a position below a lower end of each of the deep layers through intervals between the deep layers. The drain-side layer includes a high concentration layer distributed in at least a part of a depth range in which both the deep layers and the trench lower layers are present, and an intermediate concentration layer distributed in at least a part of a depth range between a lower end of the high concentration layer and a lower end of each of the deep layers.
1 . A field effect transistor comprising:
a semiconductor substrate having a plurality of trenches provided from an upper surface of the semiconductor substrate;
a gate insulating film covering an inner surface of each of the plurality of trenches;
a gate electrode disposed inside each of the plurality of trenches and being insulated from the semiconductor substrate by the gate insulating film; and
a source electrode being in contact with the upper surface of the semiconductor substrate, wherein
the semiconductor substrate includes:
a source layer of n-type being in contact with the source electrode and in contact with the gate insulating film on a side surface of each of the plurality of trenches;
a body layer of p-type being in contact with the gate insulating film at a position below the source layer;
a plurality of trench lower layers of p-type;
a plurality of deep layers of p-type; and
a drain-side layer of n-type,
each of the plurality of trench lower layers is disposed directly below a corresponding one of the plurality of trenches, extends along a longitudinal direction of the plurality of trenches when the semiconductor substrate is viewed from above, and is electrically connected to the source electrode,
each of the plurality of deep layers is disposed directly below the body layer, extends from a position above a lower end of each of the plurality of trench lower layers to a position below the lower end of each of the plurality of trench lower layers, extends along a first direction intersecting the plurality of trenches when the semiconductor substrate is viewed from above, intersects each of the plurality of trench lower layers, and is electrically connected to the source electrode,
respective deep layers in the plurality of deep layers are arranged at intervals along a second direction orthogonal to the first direction when the semiconductor substrate is viewed from above,
the drain-side layer is distributed from a position in contact with a lower surface of the body layer to a position below a lower end of each of the plurality of deep layers through each of the intervals between the deep layers, and is in contact with the gate insulating film at a position below the body layer,
the drain-side layer includes:
a high concentration layer of n-type;
an intermediate concentration layer of n-type disposed directly below the high concentration layer and having an n-type impurity concentration lower than an n-type impurity concentration of the high concentration layer; and
a drift layer of n-type disposed directly below the intermediate concentration layer and having an n-type impurity concentration lower than the n-type impurity concentration of the intermediate concentration layer,
the high concentration layer is distributed in at least a part of a depth range in which both the plurality of deep layers and the plurality of trench lower layers are present, and is in contact with a side surface of each of the plurality of trench lower layers and a side surface of each of the plurality of deep layers, and
the intermediate concentration layer is distributed in at least a part of a depth range between a lower end of the high concentration layer and the lower end of each of the plurality of deep layers, and is in contact with the side surface of each of the plurality of deep layers.
2 . The field effect transistor according to claim 1 , wherein
the high concentration layer includes:
a first layer having an n-type impurity concentration higher than the n-type impurity concentration of the intermediate concentration layer; and
a second layer having an n-type impurity concentration higher than the n-type impurity concentration of the first layer,
the second layer is disposed above the lower end of each of the plurality of trenches, and
the first layer is disposed between a lower end of the second layer and an upper end of the intermediate concentration layer.
3 . The field effect transistor according to claim 1 , wherein
a p-type impurity concentration of each of the plurality of trench lower layers is higher than a p-type impurity concentration of each of the plurality of deep layers.
4 . The field effect transistor according to claim 3 , wherein
the p-type impurity concentration of each of the plurality of deep layers is set so that a non-depleted region remains in each of the plurality of deep layers in a state where a saturation current flows through the field effect transistor.