Semiconductor structure, method of forming the semiconductor structure, and semiconductor device
A semiconductor structure, a fabricating method thereof and a semiconductor device, the structure includes a substrate having a STI region and an AA, with an upper surface of the STI region lower than an upper surface of the AA; a stacked covered on the substrate; a first insulating layer covered the stacked structure, a second insulating layer covered the first insulating layer, and a third insulating layer covered the second insulating layer, over the STI region; a first insulating layer covered the stacked structure, over the AA, with an upper surface of the first insulating layer coplanar with an upper surface of the third insulating layer. The structure provides a semiconductor structure having a flat upper surface, avoiding polishing the first insulating layer over the AA to level with the first insulating layer over the STI region, greatly increasing the leakage risk, and reducing working stability of semiconductor devices.
1 . A semiconductor structure, comprising:
a substrate, comprising an active area and a shallow trench isolation region, an upper surface of the shallow trench isolation region being lower than an upper surface of the active area;
a stacked structure, covering the upper surfaces of the active area and the shallow trench isolation region;
a first insulating layer, covered on the stacked structure, the first insulating layer simultaneously contacting the stacked structure disposed on the active area and the shallow trench isolation region;
a second insulating layer, covered on the first insulating layer disposed on the shallow trench isolation region, the second insulating layer contacting an upper surface of the first insulating layer disposed on the shallow trench isolation region; and
a third insulating layer, disposed on the second insulating layer and contacting an upper surface of the second insulating layer, an upper surface of the third insulating layer being coplanar with an upper surface of the first insulating layer disposed on the active area.
2 . The semiconductor structure according to claim 1 , wherein materials of the first insulating layer, the second insulating layer and the third insulating layer are different.
3 . The semiconductor structure according to claim 2 , wherein an etching selectivity of the third insulating layer is greater than an etching selectivity of the first insulating layer, and is smaller than an etching selectivity of the second insulating layer.
4 . The semiconductor structure according to claim 1 , wherein the stacked structure comprises:
a dielectric layer covered on the substrate;
a conductive layer disposed on the dielectric layer.
5 . The semiconductor structure according to claim 1 , wherein the semiconductor structure further comprising: an insulating spacer layer disposed on sidewalls of the stacked structure and the first insulating layer, and the second insulating layer covered the insulating spacer layer.
6 . The semiconductor structure according to claim 1 , wherein a bottommost surface of the second insulating layer is higher than an upper surface of the stack structure.
7 . A semiconductor structure, comprising:
a substrate, comprising an active area and a shallow trench isolation region, an upper surface of the shallow trench isolation region being lower than an upper surface of the active area;
a stacked structure, covering the upper surfaces of the active area and the shallow trench isolation region;
a first insulating layer, covered on the stacked structure, the first insulating layer simultaneously contacting the stacked structure disposed on the active area and the shallow trench isolation region;
a second insulating layer, covered on the first insulating layer disposed on the shallow trench isolation region, the second insulating layer contacting the first insulating layer disposed on the shallow trench isolation region;
a third insulating layer, disposed on the second insulating layer, an upper surface of the third insulating layer being coplanar with an upper surface of the first insulating layer disposed on the active area; and
an insulating spacer layer disposed on sidewalls of the stacked structure and the first insulating layer, and the second insulating layer covered the insulating spacer layer.
8 . The semiconductor structure according to claim 7 , wherein a bottommost surface of the second insulating layer is higher than an upper surface of the stack structure.
9 . The semiconductor structure according to claim 7 , wherein materials of the first insulating layer, the second insulating layer and the third insulating layer are different.
10 . The semiconductor structure according to claim 9 , wherein an etching selectivity of the third insulating layer is greater than an etching selectivity of the first insulating layer, and is smaller than an etching selectivity of the second insulating layer.
11 . The semiconductor structure according to claim 7 , wherein the stacked structure comprises:
a dielectric layer covered on the substrate;
a conductive layer disposed on the dielectric layer.