IP Library › Granted Patent US 12684833
Granted Patent B2
US 12684833 · App. 17/888,639 · Granted Jul 14, 2026

Semiconductor device

Inventors: Ho Jin Lee (Hwaseong-si, KR); Beom Jin Park (Hwaseong-si, KR); Myoung Sun Lee (Seoul, KR); Keun Hwi Cho (Seoul, KR); Dong Won Kim (Seongnam-si, KR)
Assignee: SAMSUNG ELECTRONICS CO., LTD.
H10D62/121H10D30/43H10D30/6757H10D64/021
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Quick Facts
Patent No.
US 12684833
App. No.
17/888,639
Granted
Jul 14, 2026
Kind
B2
Abstract

A semiconductor device includes first to fourth active patterns extending in a horizontal first direction. The second active pattern is spaced apart from the first active pattern in the first direction. The third active pattern is spaced apart from the first active pattern in a horizontal second direction. The fourth active pattern is spaced apart from the third active pattern in the first direction. A field insulating layer surrounds a sidewall of each of the first to fourth active patterns. First to fourth pluralities of nanosheets are respectively disposed the first to fourth active patterns. A first gate electrode extends in the second direction, intersects each of the first and third active patterns, and surrounds the first and third pluralities of nanosheets. A second gate electrode extends in the second direction, intersects each of the second and fourth active patterns, and surrounds the second and fourth pluralities of nanosheets.

Claims (58)

1 . A semiconductor device, comprising:

a first active pattern extending in a first horizontal direction;

a second active pattern extending in the first horizontal direction and spaced apart from the first active pattern in the first horizontal direction;

a third active pattern extending in the first horizontal direction and spaced apart from the first active pattern in a second horizontal direction different from the first horizontal direction;

a fourth active pattern extending in the first horizontal direction and spaced apart from the third active pattern in the first horizontal direction;

a field insulating layer surrounding a sidewall of each of the first to fourth active patterns;

a first plurality of nanosheets, a second plurality of nanosheets, a third plurality of nanosheets, and a fourth plurality of nanosheets respectively disposed on the first to fourth active patterns;

a first gate electrode extending in the second horizontal direction, intersecting each of the first and third active patterns, and surrounding each of the first and third plurality of nanosheets;

a second gate electrode extending in the second horizontal direction, intersecting each of the second and fourth active patterns, and surrounding each of the second and fourth plurality of nanosheets, wherein:

a first pitch in the first horizontal direction between the first active pattern and the second active pattern is smaller than a second pitch in the first horizontal direction between the third active pattern and the fourth active pattern,

at least a part of the first gate electrode is disposed on a portion of the field insulating layer between the third active pattern and the fourth active pattern, and

a width of the first gate electrode in the first horizontal direction of a portion overlapping the first plurality of nanosheets in the first horizontal direction is smaller than a width of the first gate electrode in the first horizontal direction of a portion overlapping the third plurality of nanosheets in the first horizontal direction.

2 . The semiconductor device as claimed in claim 1 , wherein a third pitch in the first horizontal direction between the first plurality of nanosheets and the second plurality of nanosheets is smaller than a fourth pitch in the first horizontal direction between the third plurality of nanosheets and the fourth plurality of nanosheets.

3 . The semiconductor device according to claim 1 , wherein a first width in the first horizontal direction of the field insulating layer disposed between the first active pattern and the second active pattern is smaller than a second width in the first horizontal direction of the field insulating layer disposed between the third active pattern and the fourth active pattern.

4 . The semiconductor device as claimed in claim 1 , wherein at least a part of the second gate electrode is disposed on the field insulating layer between the third active pattern and the fourth active pattern.

5 . The semiconductor device as claimed in claim 1 , wherein the second gate electrode is not disposed on the field insulating layer between the third active pattern and the fourth active pattern.

6 . The semiconductor device as claimed in claim 1 , wherein the second gate electrode is not disposed on the field insulating layer between the first active pattern and the second active pattern.

7 . The semiconductor device as claimed in claim 6 , wherein the first gate electrode is not disposed on the field insulating layer between the first active pattern and the second active pattern.

8 . The semiconductor device as claimed in claim 1 , wherein at least a part of the first gate electrode is disposed on the field insulating layer between the first active pattern and the second active pattern.

9 . The semiconductor device as claimed in claim 8 , wherein at least a part of the second gate electrode is disposed on the field insulating layer between the first active pattern and the second active pattern.

10 . The semiconductor device as claimed in claim 1 , wherein the first and the second active patterns are disposed in an NMOS region, and the third and fourth active patterns are disposed in a PMOS region.

11 . A semiconductor device, comprising:

a first active pattern extending in a first horizontal direction;

a second active pattern extending in the first horizontal direction and spaced apart from the first active pattern in the first horizontal direction;

a third active pattern extending in the first horizontal direction and spaced apart from the first active pattern in a second horizontal direction different from the first horizontal direction;

a fourth active pattern extending in the first horizontal direction and spaced apart from the third active pattern in the first horizontal direction;

a field insulating layer surrounding a sidewall of each of the first to fourth active patterns;

a first plurality of nanosheets, a second plurality of nanosheets, a third plurality of nanosheets, and a fourth plurality of nanosheets respectively disposed on the first to fourth active patterns;

a first gate electrode extending in the second horizontal direction, intersecting each of the first and third active patterns, and surrounding each of the first and third plurality of nanosheets;

a second gate electrode extending in the second horizontal direction, intersecting each of the second and fourth active patterns, and surrounding each of the second and fourth plurality of nanosheets;

a first gate spacer disposed on each of both opposing sidewalls of the first gate electrode and extending in the second horizontal direction; and

a second gate spacer disposed on each of both opposing sidewalls of the second gate electrode and extending in the second horizontal direction, wherein:

a first width in the first horizontal direction of the field insulating layer disposed between the first active pattern and the second active pattern is smaller than a second width in the first horizontal direction of the field insulating layer disposed between the third active pattern and the fourth active pattern,

a first pitch in the first horizontal direction between the first plurality of nanosheets and the second plurality of nanosheets is smaller than a second pitch in the first horizontal direction between the third plurality of nanosheets and the fourth plurality of nanosheets, and

a width of the first gate electrode in the first horizontal direction of a portion overlapping the first plurality of nanosheets in the first horizontal direction is smaller than a width of the first gate electrode in the first horizontal direction of a portion overlapping the third plurality of nanosheets in the first horizontal direction.

12 . The semiconductor device as claimed in claim 11 , wherein at least a part of the first gate electrode is disposed on the field insulating layer between the third active pattern and the fourth active pattern.

13 . The semiconductor device as claimed in claim 12 , wherein at least a part of the second gate electrode is disposed on the field insulating layer between the third active pattern and the fourth active pattern.

14 . The semiconductor device as claimed in claim 11 , wherein each of the first and second gate spacers is disposed on the field insulating layer between the first plurality of nanosheets and the second plurality of nanosheets and on the field insulating layer between the third plurality of nanosheets and the fourth plurality of nanosheets.

15 . The semiconductor device as claimed in claim 11 , wherein, in a region between the first active pattern and the second active pattern, one sidewall of the second gate spacer facing the second gate electrode is aligned with a sidewall of the second active pattern in a vertical direction perpendicular to the first and second horizontal directions.

16 . The semiconductor device as claimed in claim 11 , wherein, in a region between the third active pattern and the fourth active pattern, one sidewall of the second gate spacer facing the second gate electrode is aligned with a sidewall of the fourth active pattern in a vertical direction perpendicular to the first and second horizontal directions.

17 . The semiconductor device as claimed in claim 11 , wherein at least a part of the first gate electrode is disposed on the field insulating layer between the first active pattern and the second active pattern.

18 . The semiconductor device as claimed in claim 17 , wherein at least a part of the second gate electrode is disposed on the field insulating layer between the first active pattern and the second active pattern.

19 . The semiconductor device as claimed in claim 11 , wherein the second gate spacer is in contact with a sidewall of the second plurality of nanosheets between the first plurality of nanosheets and the second plurality of nanosheets.

20 . A semiconductor device, comprising:

a substrate having an NMOS region and a PMOS region defined therein;

a first active pattern extending in a first horizontal direction and disposed on the NMOS region;

a second active pattern extending in the first horizontal direction and disposed on the NMOS region, wherein the second active pattern is spaced apart from the first active pattern in the first horizontal direction;

a third active pattern extending in the first horizontal direction and disposed on the PMOS region, wherein the third active pattern is spaced apart from the first active pattern in a second horizontal direction different from the first horizontal direction;

a fourth active pattern extending in the first horizontal direction and disposed on the PMOS region, wherein the fourth active pattern is spaced apart from the third active pattern in the first horizontal direction;

a field insulating layer surrounding a sidewall of each of the first to fourth active patterns;

a first plurality of nanosheets, a second plurality of nanosheets, a third plurality of nanosheets, and a fourth plurality of nanosheets respectively disposed on the first to fourth active patterns;

a first gate electrode extending in the second horizontal direction, intersecting each of the first and third active patterns, and surrounding each of the first and third plurality of nanosheets; and

a second gate electrode extending in the second horizontal direction, intersecting each of the second and fourth active patterns, and surrounding each of the second and fourth plurality of nanosheets, wherein:

a first pitch in the first horizontal direction between the first active pattern and the second active pattern is smaller than a second pitch in the first horizontal direction between the third active pattern and the fourth active pattern,

a third pitch in the first horizontal direction between the first plurality of nanosheets and the second plurality of nanosheets is smaller than a fourth pitch in the first horizontal direction between the third plurality of nanosheets and the fourth plurality of nanosheets,

each of the first gate electrode and the second gate electrode is not disposed on the field insulating layer between the first active pattern and the second active pattern, and

each of at least a part of the first gate electrode and at least a part of the second gate electrode is disposed on the field insulating layer between the third active pattern and the fourth active pattern, and

a width of the first gate electrode in the first horizontal direction of a portion overlapping the first plurality of nanosheets in the first horizontal direction is smaller than a width of the first gate electrode in the first horizontal direction of a portion overlapping the third plurality of nanosheets in the first horizontal direction.