Complementary field effect transistor with conductive through substrate layer
A device includes: a complementary transistor including: a first transistor having first and second source/drain regions; and a second transistor stacked on the first transistor, and having a third source/drain region and a fourth source/drain region, the third source/drain region overlapping the first source/drain region, the fourth source/drain region overlapping the second source/drain region. The device further includes: a first source/drain contact electrically coupled to the third source/drain region; a second source/drain contact electrically coupled to the second source/drain region; a gate isolation structure adjacent the first and second transistors; and an interconnect structure electrically coupled to the first source/drain contact and the second source/drain contact. The interconnect structure includes: a conductive layer in contact with the first source/drain contact and the second source/drain contact, the conductive layer being in the gate isolation structure; an opening in the conductive layer; and a dielectric layer in the opening.
1 . A method, comprising:
forming a first transistor and a second transistor stacked on the first transistor;
forming a first opening adjacent the first transistor and the second transistor;
forming a gate isolation layer in the first opening;
forming a conductive layer on the gate isolation layer, the conductive layer being in the first opening;
forming a cutout region in the conductive layer;
forming a dielectric layer on the conductive layer in the cutout region;
forming a frontside source/drain contact in contact with the second transistor and the conductive layer; and
forming a backside source/drain contact in contact with the first transistor and the conductive layer.
2 . The method of claim 1 , wherein the cutout region is rectangular.
3 . The method of claim 1 , wherein the cutout region is triangular.
4 . The method of claim 1 , wherein the forming a gate isolation layer includes:
forming a first dielectric layer in the first opening; and
forming a second dielectric layer on the first dielectric layer, the second dielectric layer having a higher dielectric constant than the first dielectric layer.
5 . The method of claim 1 , wherein the forming a frontside source/drain contact includes:
forming a second opening that exposes a source/drain region of the second transistor, recesses a portion of the gate isolation layer, and exposes an upper surface of the conductive layer; and
forming the frontside source/drain contact in the second opening.
6 . The method of claim 1 , further comprising:
forming a second frontside source/drain contact that lands on the dielectric layer.
7 . A method, comprising:
forming a first transistor and a second transistor stacked on the first transistor;
forming a first opening adjacent the first transistor and the second transistor;
forming a gate isolation layer in the first opening;
forming a conductive layer on the gate isolation layer, the conductive layer being in the first opening;
forming a frontside source/drain contact in contact with the second transistor and an upper surface of the conductive layer;
forming a cutout region in the conductive layer after the forming a frontside source/drain contact;
forming a dielectric layer on the conductive layer in the cutout region; and
forming a backside source/drain contact in contact with the first transistor and the conductive layer.
8 . The method of claim 7 , wherein the forming the cutout region comprises:
removing a portion of the conductive layer that overlaps respective gate metals of the first transistor and the second transistor.
9 . The method of claim 7 , wherein the forming the cutout region comprises:
etching the conductive layer from a side of the conductive layer vertically opposite the frontside source/drain contact.
10 . The method of claim 9 , wherein the conductive layer has a tapered sidewall following the etching.
11 . A method, comprising:
forming a first transistor and a second transistor stacked on the first transistor;
forming a first opening adjacent the first transistor and the second transistor;
forming a gate isolation layer in the first opening;
forming a lower portion of a conductive layer in a bottom portion of the first opening;
forming a dielectric layer in the first opening on the lower portion of the conductive layer;
forming a second opening in the dielectric layer that exposes the lower portion of the conductive layer;
forming an upper portion of the conductive layer in the second opening and in contact with the lower portion;
forming a frontside source/drain contact in contact with the upper portion; and
forming a backside source/drain contact in contact with the lower portion.
12 . The method of claim 11 , wherein the second opening is narrower than the first opening in a horizontal direction.
13 . The method of claim 11 , further comprising performing a chemical mechanical planarization process to remove excess material of the upper portion from an upper surface of the dielectric layer.
14 . The method of claim 11 , wherein the dielectric layer comprises a low-k dielectric material.
15 . The method of claim 11 , further comprising forming a second frontside source/drain contact that lands on the dielectric layer.
16 . The method of claim 11 , wherein forming the gate isolation layer includes forming a liner layer having a lower dielectric constant than the gate isolation layer.
17 . The method of claim 11 , wherein the lower portion and the upper portion are formed of one or more of W, Co, Cu, or Ru.
18 . The method of claim 11 , wherein the lower portion has a vertical height that is less than about 100 nm.
19 . The method of claim 11 , wherein the first transistor is an N-type transistor and the second transistor is a P-type transistor.
20 . The method of claim 11 , further comprising forming a silicide layer between the frontside source/drain contact and a source/drain region of the second transistor.