Semiconductor integrated circuit device
A layout structure of a capacitive cell using forksheet FETs is provided. In transistors P 3 and N 3 , VDD is supplied to a pair of pads 22 c, 22 d and a gate interconnect 36 c , and VSS is supplied to a pair of pads 27 c, 27 d and a gate interconnect 31 c . Capacitances are produced between nanosheets 21 c and the gate interconnect 31 c and between nanosheets 26 c and the gate interconnect 36 c . The faces of the nanosheets 21 c closer to the nanosheets 26 c are exposed from the gate interconnect 31 c , and the faces of the nanosheets 26 c closer to the nanosheets 21 c are exposed from the gate interconnect 36 c.
1 . A semiconductor integrated circuit device including a standard cell that is a capacitive cell, the standard cell having a first region in which first conductivity type transistors are formed and a second region in which second conductivity type transistors are formed lying adjacent to each other in a first direction, comprising:
a first nanosheet extending in a second direction vertical to the first direction in the first region;
a second nanosheet extending in the second direction in the second region;
a first gate interconnect extending in the first direction, formed to surround a periphery of the first nanosheet in the first direction and a third direction perpendicular to the first and second directions;
a first pair of pads each connected with each end of the first nanosheet in the second direction;
a second gate interconnect extending in the first direction, formed to surround a periphery of the second nanosheet in the first direction and the third direction; and
a second pair of pads each connected with each end of the second nanosheet in the second direction,
wherein
the first pair of pads are supplied with a first power supply voltage, and the first gate interconnect is supplied with a second power supply voltage different from the first power supply voltage, and
the first nanosheet and the second nanosheet are opposed to each other in the first direction, the first nanosheet is exposed from the first gate interconnect on a face at either one of first and second sides in the first direction, and the second nanosheet is exposed from the second gate interconnect on a face at the other one of the first and second sides in the first direction.
2 . The semiconductor integrated circuit device of claim 1 , wherein
each of the first and second nanosheets is constituted by a stacked structure of a plurality of nanosheets overlapping as viewed in plan.
3 . The semiconductor integrated circuit device of claim 1 , wherein
the first and second gate interconnects are placed at a same position in the second direction.
4 . The semiconductor integrated circuit device of claim 1 , comprising:
a first power line extending in the second direction, supplying the first power supply voltage;
a second power line extending in the second direction, supplying the second power supply voltage; and
a fixed value output unit connected with the first and second power lines, supplying the second power supply voltage to the first gate interconnect,
wherein
the fixed value output unit includes
a first transistor of the first conductivity type formed in the first region, connected with the first power line at its source, and
a second transistor of the second conductivity type formed in the second region, connected with the second power line at its source,
the first gate interconnect is electrically connected with a gate of the first transistor and a drain of the second transistor, and
a drain of the first transistor is connected with a gate of the second transistor.
5 . The semiconductor integrated circuit device of claim 1 , wherein
the second pair of pads are supplied with the second power supply voltage, and the second gate interconnect is supplied with the first power supply voltage.
6 . The semiconductor integrated circuit device of claim 1 , wherein
the second gate interconnect is supplied with the second power supply voltage.