Structure and related method for source/drain terminal within subcollector
The disclosure provides structures and related methods to provide a source/drain (S/D) terminal within a subcollector. A structure according to the disclosure includes a field effect transistor (FET) structure having a source/drain (S/D) terminal within a semiconductor layer, and a gate structure on the semiconductor layer. A bipolar transistor (BT) structure is on the FET structure and includes a subcollector within the semiconductor layer, and a collector-base-emitter stack on the subcollector and above the semiconductor layer.
1 . A structure comprising:
a field effect transistor (FET) structure including:
a source/drain (S/D) terminal within a semiconductor layer, and
a gate structure on the semiconductor layer;
a bipolar transistor (BT) structure on the FET structure, the BT structure including:
a subcollector within the semiconductor layer, and
a collector-base-emitter stack on the subcollector and above the semiconductor layer; and
an intra-terminal insulator within a portion of the S/D terminal distal to the collector-base-emitter stack wherein the S/D terminal horizontally surrounds the intra-terminal insulator.
2 . The structure of claim 1 , wherein the subcollector is coextensive with the S/D terminal.
3 . The structure of claim 1 , wherein a lower surface of the subcollector is below a lower surface of the S/D terminal.
4 . The structure of claim 3 , further comprising a silicide layer partially within the S/D terminal and partially within the subcollector.
5 . The structure of claim 1 , wherein the gate structure includes:
a gate conductor over the semiconductor layer; and
a spacer horizontally between the gate conductor and the collector-base-emitter stack.
6 . The structure of claim 1 , further comprising an additional FET structure including:
an additional gate structure over the semiconductor layer, wherein the BT structure is horizontally between the gate structure and the additional gate structure; and
an additional S/D terminal within the semiconductor layer.
7 . The structure of claim 6 , wherein the subcollector is coextensive with the S/D terminal and the additional S/D terminal.
8 . A structure comprising:
a field effect transistor (FET) structure including:
a source/drain (S/D) terminal within a semiconductor layer, and
a gate structure on the semiconductor layer;
a bipolar transistor (BT) structure on the FET structure, the BT structure including:
a subcollector within the semiconductor layer, wherein the S/D terminal is coextensive with the subcollector, and
a collector-base-emitter stack on the subcollector and above the semiconductor layer, wherein the collector-base-emitter stack is horizontally adjacent the gate structure; and
an intra-terminal insulator within a portion of the S/D terminal distal to the collector-base-emitter stack wherein the S/D terminal horizontally surrounds the intra-terminal insulator.
9 . The structure of claim 8 , wherein the gate structure includes:
a gate conductor over the semiconductor layer;
a first gate dielectric layer vertically between the semiconductor layer and the gate conductor; and
a second gate dielectric layer horizontally between the gate conductor and the collector-base-emitter stack.
10 . The structure of claim 8 , wherein a length of the S/D terminal is greater than a length of the collector-base-emitter stack.
11 . The structure of claim 8 , wherein the subcollector is free of conductive contacts thereon.
12 . The structure of claim 8 , further comprising:
an additional gate structure over the semiconductor layer, wherein the collector-base-emitter stack is horizontally between the gate structure and the additional gate structure; and
an additional S/D terminal within the semiconductor layer, wherein the additional gate structure is between the subcollector and the additional S/D terminal.
13 . The structure of claim 12 , wherein the additional S/D terminal has a same doping profile as the subcollector and the S/D terminal.
14 . The structure of claim 12 , wherein the subcollector is coextensive with the S/D terminal and the additional S/D terminal.
15 . A method comprising:
forming a field effect transistor (FET) structure including:
a source/drain (S/D) terminal within a semiconductor layer, and
a gate structure on the semiconductor layer;
forming a bipolar transistor (BT) structure on the FET structure, the BT structure including:
a subcollector within the semiconductor layer, and
a collector-base-emitter stack on the subcollector and above the semiconductor layer; and
forming an intra-terminal insulator within a portion of the S/D terminal distal to the collector-base-emitter stack wherein the S/D terminal horizontally surrounds the intra-terminal insulator.
16 . The method of claim 15 , wherein forming the BT structure causes the subcollector to be coextensive with the S/D terminal.
17 . The method of claim 15 , further comprising forming a silicide layer partially within the S/D terminal and partially within the subcollector, wherein a lower surface of the subcollector is below a lower surface of S/D terminal.
18 . The method of claim 15 , wherein forming the gate structure includes:
forming a gate conductor over the semiconductor layer; and
forming a spacer horizontally between a gate conductor and the collector-base-emitter stack.
19 . The method of claim 15 , further comprising forming an additional FET structure including:
an additional gate structure over the semiconductor layer, wherein the BT structure is horizontally between the gate structure and the additional gate structure; and
an additional S/D terminal within the semiconductor layer.
20 . The method of claim 19 , wherein forming the additional FET structure causes the subcollector to be coextensive with the S/D terminal and the additional S/D terminal.