IP Library Granted Patent US 12684839
Granted Patent B2
US 12684839 · App. 18/117,262 · Granted Jul 14, 2026

Semiconductor device

Inventors: Ki Hwan Kim (Suwon-si, KR); Kyung Ho Kim (Suwon-si, KR); Kang Hun Moon (Suwon-si, KR); Cho Eun Lee (Suwon-si, KR); Yong Uk Jeon (Suwon-si, KR)
Assignee: SAMSUNG ELECTRONICS CO., LTD.
H10D62/151H10D30/014H10D30/43H10D30/6735H10D62/121H10D64/017H10D64/679H10D84/85
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Quick Facts
Patent No.
US 12684839
App. No.
18/117,262
Granted
Jul 14, 2026
Kind
B2
Abstract

A semiconductor device comprises an active pattern including a lower pattern and a plurality of sheet patterns that are spaced apart from the lower pattern in a first direction, a plurality of gate structures disposed on the lower pattern to be spaced apart from each other in a second direction, each of the gate structures including a gate electrode and gate insulating films, source/drain recesses defined between adjacent gate structures and a source/drain pattern filling the source/drain recesses. Each source/drain pattern may include a first semiconductor liner, which extend along sidewalls and a bottom surface of the source/drain recesses, second semiconductor liners, which are on the first semiconductor liners and extend along the sidewalls and the bottom surface of the source/drain recesses, and a filling semiconductor film, which is on the second semiconductor liners and fills the source/drain recess. The second semiconductor liners may be doped with carbon, and the first semiconductor liners may be in contact with the lower pattern and the sheet patterns, while the first semiconductor liners may include carbon-undoped regions.

Claims (63)

1 . A semiconductor device comprising:

an active pattern including a lower pattern and a plurality of sheet patterns, which are spaced apart from the lower pattern in a first direction;

a plurality of gate structures disposed on the lower pattern and spaced apart from each other in a second direction, each of the gate structures including a gate electrode and gate insulating film;

source/drain recesses, each defined between a corresponding pair of the gate structures that are adjacent to each other; and

source/drain patterns, each filling a corresponding one of the source/drain recesses,

wherein each of the source/drain patterns include a first semiconductor liner that is continuous and extends along sidewalls and a bottom surface of the corresponding source/drain recess, a second semiconductor liner on the first semiconductor liner, the second semiconductor liner being continuous and extending adjacent to the sidewalls and the bottom surface of the corresponding source/drain recess, and a filling semiconductor film on the second semiconductor liner that fills the corresponding source/drain recess,

wherein the second semiconductor liners are doped with carbon,

wherein each of the first semiconductor liners are in contact with the lower pattern and at least two of the sheet patterns that are spaced apart from each other in the first direction,

wherein the first semiconductor liners include carbon-undoped regions,

wherein the first semiconductor liners include carbon-diffused regions, which extend along the sidewalls and the bottom surface of each of the source/drain recesses,

wherein the carbon-diffused regions are disposed between corresponding ones of the carbon-undoped regions and the second semiconductor liners,

wherein carbon concentrations of the carbon-diffused regions increase in a direction away from the corresponding carbon-undoped region, and

wherein the first semiconductor liners and the second semiconductor liners are formed of a corresponding crystalline semiconductor material.

2 . The semiconductor device of claim 1 , wherein each carbon-undoped region is continuously formed along the sidewalls and the bottom surface of a corresponding one of the source/drain recesses.

3 . The semiconductor device of claim 1 , wherein each first semiconductor liner comprises a plurality of the carbon-undoped regions that are discretely formed and separated from another, including first and second sub-carbon-undoped regions, which are spaced apart from each other in the first direction.

4 . The semiconductor device of claim 1 , wherein

each of the gate structures includes inner gate structures, each being disposed between a corresponding pair of adjacent sheet patterns or between the lower pattern and the sheet patterns adjacent to the lower pattern, the inner gate structures including a corresponding portion of the gate electrode of the gate structure and a corresponding one of the gate insulating films of the gate structure, and

the first semiconductor liners are in contact with the gate insulating films of corresponding ones of the inner gate structures.

5 . The semiconductor device of claim 1 , wherein each filling semiconductor film is doped with phosphorus and is in contact with a corresponding one of the second semiconductor liners.

6 . The semiconductor device of claim 1 , wherein

each source/drain pattern further comprises a third semiconductor liner, which is disposed between the second semiconductor liner and the filling semiconductor film of the source/drain pattern, the filling semiconductor film being doped with a first n-type impurities, and the third semiconductor liners being doped with second n-type impurities that are different from the first n-type impurities.

7 . The semiconductor device of claim 1 , wherein the filling semiconductor films and the first semiconductor liners are doped with boron.

8 . The semiconductor device of claim 1 , wherein each of the first semiconductor liners and the second semiconductor liners includes a silicon film or a silicon-germanium film.

9 . A semiconductor device comprising:

an active pattern including a lower pattern and a plurality of sheet patterns, which are spaced apart from the lower pattern in a first direction;

a plurality of gate structures disposed on the lower pattern and spaced apart from each other in a second direction, each of the gate structures including a gate electrode and gate insulating films;

source/drain recesses, each defined between a corresponding pair of the gate structures that are adjacent to each other, each of the source/drain recesses including a plurality of width-expanded regions; and

source/drain patterns, each filling a corresponding one of the source/drain recesses,

wherein each of the gate structures includes inner gate structures each being disposed between a corresponding pair of adjacent sheet patterns or between the lower pattern and the sheet pattern adjacent to the lower pattern, the inner gate structures including a corresponding portion of the gate electrode and a corresponding one of the gate insulating films of the gate structure,

wherein each of the source/drain pattern includes a first semiconductor liner that is continuous and extends along sidewalls and a bottom surface of the corresponding source/drain recess, a second semiconductor liner on the first semiconductor liner, the second semiconductor liner being continuous and extending adjacent to the sidewalls and the bottom surface of the corresponding source/drain recess, and a filling semiconductor film on the second semiconductor liner that is doped with phosphorus,

wherein each second semiconductor liner is disposed between a corresponding first semiconductor liner and a corresponding filling semiconductor film and is doped with carbon,

wherein each of the first semiconductor liners include one or more carbon-undoped regions that are in contact with the gate insulating films of the inner gate structures of a corresponding one of the gate structures,

wherein a width, in the second direction, of each of the width-expanded regions increases and then decreases with respect to a direction away from an upper surface of the lower pattern and is maximum at a location between a corresponding pair of vertically adjacent sheet patterns or between the lower pattern and the sheet pattern vertically adjacent the lower pattern,

wherein each of the first semiconductor liners are in contact with the lower pattern and at least two of the sheet patterns that are spaced apart from each other in the first direction, and

wherein the first semiconductor liners and the second semiconductor liners are formed of a corresponding crystalline semiconductor material.

10 . The semiconductor device of claim 9 , wherein each carbon-undoped region comprises all of a corresponding one of the first semiconductor liners.

11 . The semiconductor device of claim 9 , wherein each carbon-undoped region is continuously formed along the sidewalls and the bottom surface of a corresponding one of the source/drain recesses.

12 . The semiconductor device of claim 11 , wherein

the first semiconductor liners include carbon-diffused regions, which extend along the sidewalls and the bottom surface of the source/drain recesses,

the carbon-diffused regions are disposed between corresponding ones of the carbon-undoped regions and the second semiconductor liners, and

carbon concentrations of the carbon-diffused regions increase in a direction away from the corresponding carbon-undoped regions.

13 . The semiconductor device of claim 9 , wherein

each source/drain pattern further comprises a third semiconductor liner disposed between the second semiconductor liner and the filling semiconductor film of the source/drain pattern, the third semiconductor liner being doped with n-type impurities, and the n-type impurities including at least one of arsenic, antimony, or bismuth.

14 . The semiconductor device of claim 9 , wherein for each source/drain pattern, the corresponding filling semiconductor film is in contact with the corresponding second semiconductor liner.

15 . The semiconductor device of claim 9 , wherein the filling semiconductor film of at least one of the source/drain patterns includes an airgap.

16 . A semiconductor device comprising:

a first active pattern including a first lower pattern and a plurality of first sheet patterns, which are spaced apart from the first lower pattern in a first direction;

a second active pattern including a second lower pattern and a plurality of second sheet patterns, which are spaced apart from the second lower pattern in the first direction;

a plurality of first gate structures disposed on the first lower pattern and spaced apart from each other in a second direction, each of the first gate structures including a first gate electrode and first gate insulating films;

a plurality of second gate structures disposed on the second lower pattern and spaced apart from each other in the second direction, each of the second gate structures including a second gate electrode and second gate insulating films;

first source/drain recesses, each defined between a corresponding pair of the first gate structures that are adjacent to each other;

second source/drain recesses, each defined between a corresponding pair of the second gate structures that are adjacent to each other;

first source/drain patterns, each disposed in a corresponding one of the first source/drain recesses, each of the first source/drain patterns being in contact with the first gate insulating films of a corresponding first gate structure and the first lower pattern; and

second source/drain patterns, each disposed in a corresponding one the second source/drain recesses, each of the second source/drain patterns being in contact with the second gate insulating films of a corresponding second gate structure and the second lower pattern and including p-type impurities,

wherein each of the first source/drain patterns includes a first lower semiconductor liner that is continuous and extends along sidewalls and a bottom surface of the corresponding first source/drain recess, a first upper semiconductor liner on the first lower semiconductor liner, the first upper semiconductor liner being continuous and extending adjacent to the sidewalls and the bottom surface of the corresponding first source/drain recess, and a first filling semiconductor film doped with phosphorous and on the first upper semiconductor liner,

wherein the first upper semiconductor liners each include a silicon film doped with carbon,

wherein the first lower semiconductor liners are in contact with the first lower pattern and at least two of the first sheet patterns that are spaced apart from each other in the first direction and include carbon-undoped regions, which extend along the sidewalls and the bottom surface of the corresponding first source/drain recesses,

wherein the second source/drain patterns do not include carbon-doped semiconductor liners extending along the sidewalls and the bottom surface of the second source/drain recesses, and

wherein the first lower semiconductor liners and the first upper semiconductor liners are formed of a corresponding crystalline semiconductor material.

17 . The semiconductor device of claim 16 , wherein, for each first source/drain pattern, the corresponding first upper semiconductor liner is in contact with the corresponding first filling semiconductor film.

18 . The semiconductor device of claim 16 , wherein

each of the first source/drain patterns further includes an additional semiconductor liner disposed between the first filling semiconductor film and the first upper semiconductor liner, and

the additional semiconductor liners are doped with arsenic.