Gate structure on intrinsic base layer and overhanging lateral sidewall of intrinsic base layer
A structure including a first emitter-collector (E/C) layer over a substrate. The structure further includes an intrinsic base layer over the first E/C layer and a second E/C layer over the intrinsic base layer. The structure includes an extrinsic base layer on the intrinsic base layer and adjacent the second E/C layer. The structure includes a gate structure on the intrinsic base layer and overhanging a lateral sidewall of the intrinsic base.
1 . A structure, comprising:
a first emitter-collector (E/C) layer over a substrate;
an intrinsic base layer over the first E/C layer;
a second E/C layer over the intrinsic base layer;
an extrinsic base layer on the intrinsic base layer and adjacent the second E/C layer; and
a gate structure on the intrinsic base layer and overhanging a lateral sidewall of the intrinsic base layer.
2 . The structure of claim 1 , wherein an upper surface of the gate structure is above an upper surface of the extrinsic base layer.
3 . The structure of claim 1 , further comprising a trench isolation structure adjacent the intrinsic base layer and below the gate structure.
4 . The structure of claim 1 , wherein the gate structure includes one of a polycrystalline semiconductor, a metal, and a high-k material.
5 . The structure of claim 1 , wherein the gate structure further includes:
a gate stack, including:
a gate dielectric over the lateral sidewall of the intrinsic base, and
a gate conductor over the gate dielectric; and
a pair of spacers on either side of the gate stack.
6 . The structure of claim 1 , wherein the gate structure surrounds the second E/C layer.
7 . The structure of claim 6 , wherein the extrinsic base layer is between the second E/C layer and the gate structure.
8 . The structure of claim 1 , further comprising:
an E/C terminal on the first E/C layer and laterally distal to the intrinsic base layer;
an E/C contact on the E/C terminal; and
an additional gate structure on the E/C terminal and overhanging a lateral sidewall of the E/C terminal.
9 . A structure, comprising:
a first emitter-collector (E/C) layer over a substrate;
an intrinsic base layer over the first E/C layer;
a second E/C layer over the intrinsic base layer;
an extrinsic base layer on the intrinsic base layer and adjacent the second E/C layer;
an E/C terminal on the first E/C layer and laterally distal to the intrinsic base layer; and
a gate structure on the E/C terminal and overhanging a lateral sidewall of E/C terminal.
10 . The structure of claim 9 , wherein the gate structure includes one of a polycrystalline semiconductor, a metal, and a high-k material.
11 . The structure of claim 9 , wherein the gate structure further includes:
a gate stack, including:
a gate dielectric over the lateral sidewall of the intrinsic base, and
a gate conductor over the gate dielectric; and
a pair of spacers on either side of the gate stack.
12 . The structure of claim 9 , wherein the E/C terminal includes an epitaxially-grown semiconductor.
13 . The structure of claim 9 , wherein the E/C terminal includes silicon germanium.
14 . The structure of claim 9 , wherein the gate structure surrounds the second E/C layer.
15 . The structure of claim 14 , further comprising an additional gate structure overhanging a lateral sidewall of the intrinsic base layer.
16 . A method, comprising:
forming a first emitter-collector (E/C) layer over a substrate;
forming an intrinsic base layer over the first E/C layer;
forming a second E/C layer over the intrinsic base layer;
forming an extrinsic base layer on the intrinsic base layer and adjacent the second E/C layer; and
forming a gate structure on the intrinsic base layer and overhanging a lateral sidewall of the intrinsic base layer.
17 . The method of claim 16 , wherein an upper surface of the gate structure is above an upper surface of the extrinsic base layer.
18 . The method of claim 16 , further comprising a trench isolation structure adjacent the intrinsic base layer and below the gate structure.
19 . The method of claim 16 , wherein the gate structure includes one of a polycrystalline semiconductor, a metal, and a high-k material.
20 . The method of claim 16 , wherein the gate structure further includes:
a gate stack, including:
a gate dielectric over the lateral sidewall of the intrinsic base layer, and
a gate conductor over the gate dielectric; and
a pair of spacers on either side of the gate stack.