Power semiconductor device and method for manufacturing the same
A power semiconductor device includes a semiconductor layer formed of silicon carbide (SiC), a trench formed by etching the semiconductor layer, a gate formed in a manner that a partial region of the gate is buried in the trench and another partial region of the gate extends over the semiconductor layer, a shield region formed to surround a lower region of the trench, a well region disposed in the semiconductor layer to be in contact with a first side surface of the trench and an upper surface of the semiconductor layer, a source region disposed in the well region, and a shield connector formed to extend from an upper surface of the semiconductor layer to the shield region while contacting a second side surface opposite to the first side surface.
1 . A power semiconductor device comprising:
a semiconductor layer including silicon carbide (SIC);
a trench in the semiconductor layer;
a gate having a first region buried in the trench and a second region extending over the semiconductor layer;
a shield region surrounding a lower region of the trench;
a well region disposed in the semiconductor layer to be in contact with a first side surface of the trench and an upper surface of the semiconductor layer;
a source region disposed in the well region to contact with the first side surface of the trench; and
a shield connector extending from the upper surface of the semiconductor layer to the shield region while contacting a second side surface opposite to the first side surface of the trench,
wherein the second region of the gate covers top surfaces of the source region and the well region as a whole.
2 . The power semiconductor device according to claim 1 , wherein the first region includes a recess gate buried in the trench and configured to form a vertical channel in the well region when operation power is received; and
the second region includes a planar gate disposed over the semiconductor layer to be connected to the recess gate and configured to form a horizontal channel in the well region when the operation power is received.
3 . The power semiconductor device according to claim 2 , wherein:
the planar gate extends to cover the well region and the source region while connected to a partial region adjacent to the source region from an upper surface of the recess gate.
4 . The power semiconductor device according to claim 1 , wherein:
the shield region is disposed in a manner such that the shield region protrudes from opposing sides of the trench in opposing directions, and both sides of the shield region are symmetrical with respect to the trench.
5 . The power semiconductor device according to claim 1 , wherein the shield region includes:
a first shield region including impurities at a first concentration; and
a second shield region including impurities at a second concentration lower than the first concentration while surrounding the first shield region.
6 . The power semiconductor device according to claim 1 , wherein the shield connector includes:
a first impurity region connected to the shield region and protrudes from the shield region toward the second side surface of the trench;
a second impurity region connected to an upper region of the first impurity region and extends to the upper surface of the semiconductor layer; and
a third impurity region disposed to contact the upper surface of the semiconductor layer in the second impurity region and includes impurities having a higher concentration than the first and second impurity regions.
7 . The power semiconductor device according to claim 1 , further comprising:
a junction field effect transistor (JFET) region disposed between the well region and the shield region in the semiconductor layer.
8 . The power semiconductor device according to claim 1 , wherein the semiconductor layer includes:
a silicon carbide (SiC) substrate; and
a silicon carbide (SiC) epitaxial layer.
9 . The power semiconductor device according to claim 8 , wherein the silicon carbide (SiC) epitaxial layer includes:
a field stopper; and
a drift region disposed over the field stopper.
10 . The power semiconductor device according to claim 1 , further comprising:
a drain electrode disposed under the semiconductor layer; and
a source electrode disposed over the gate and the semiconductor layer to be connected to the shield connector.
11 . A method for manufacturing a power semiconductor device comprising:
forming a shield region by implanting impurities of a second conductivity type opposite to a first conductivity type into a semiconductor layer including silicon carbide (SiC) having the first conductivity type;
forming a trench extending to an upper region of the shield region by etching the semiconductor layer;
forming a shield connector connecting the shield region to an upper surface of the semiconductor layer by implanting impurities of the second conductivity type into one side of the trench;
forming a well region spaced apart from the shield region by implanting the impurities of the second conductivity type into another side opposite to the one side of the trench;
forming a source region by implanting impurities of the first conductivity type into the well region to contact with the first side surface of the trench; and
forming a gate in a manner such that a partial region of the gate is buried in the trench and another partial region of the gate extends over the semiconductor layer,
wherein the source region is disposed to contact with a sidewall of the trench, and
the another partial region of the gate covers top surfaces of the source region and the well region as a whole.
12 . The method according to claim 11 , wherein the forming of the shield region includes:
forming a double shield structure including an impurity region having a first concentration of the impurities of the second conductivity type, the impurity region is surrounded by another impurity region having a second concentration of the impurities of the second conductivity type lower than the first concentration.
13 . The method according to claim 11 , wherein the forming of the trench includes:
etching the semiconductor layer to a position where a lower region of the trench is surrounded by the shield region.
14 . The method according to claim 11 , wherein the forming of the shield connector includes:
forming a first impurity region that is connected to the shield region and protrudes only in one direction from the shield region;
forming a second impurity region that is connected to the first impurity region and extends to the upper surface of the semiconductor layer; and
forming a third impurity region in the second impurity region to be in contact with the upper surface of the semiconductor layer.
15 . The method according to claim 14 , wherein:
the third impurity region has a concentration of the impurities of the second conductivity type higher than that of the second impurity region.