Selective High-K formation in gate-last process
A method includes removing a dummy gate stack to form an opening between gate spacers, selectively forming an inhibitor film on sidewalls of the gate spacers, with the sidewalls of the gate spacers facing the opening, and selectively forming a dielectric layer over a surface of a semiconductor region. The inhibitor film inhibits growth of the dielectric layer on the inhibitor film. The method further includes removing the inhibitor film, and forming a replacement gate electrode in a remaining portion of the opening.
1 . A method comprising:
removing a dummy gate stack to form an opening between gate spacers, wherein a surface of a semiconductor region is exposed to the opening as an exposed top surface of the semiconductor region;
forming an inhibitor film contacting sidewalls and top surfaces of the gate spacers;
forming a dielectric interfacial layer in the opening and contacting the exposed top surface of the semiconductor region;
after the inhibitor film is formed, in a deposition process, selectively depositing a high-k dielectric layer over and contacting the dielectric interfacial layer, wherein the high-k dielectric layer, as deposited, is free from portions on the sidewalls of the gate spacers, and is free from portions over the gate spacers;
removing a portion of the inhibitor film; and
forming a replacement gate electrode in a remaining portion of the opening that remains after the deposition process, wherein a residue portion of the inhibitor film remains underlying the replacement gate electrode.
2 . The method of claim 1 , wherein the high-k dielectric layer is selectively deposited at a bottom of the opening.
3 . The method of claim 1 , wherein the dielectric interfacial layer is formed after the inhibitor film is formed.
4 . The method of claim 1 , wherein the removing the inhibitor film comprises a thermal treatment process.
5 . The method of claim 1 , wherein at a time after the replacement gate electrode is formed, a void is formed to separate the dielectric interfacial layer from a respective closest gate spacer in the gate spacers.
6 . The method of claim 5 , wherein the replacement gate electrode overlaps the void.
7 . A method comprising:
removing a dummy gate stack to form an opening between gate spacers, wherein a surface of a semiconductor region is exposed to the opening as an exposed top surface of the semiconductor region;
forming an inhibitor film contacting sidewalls and top surfaces of the gate spacers;
after the inhibitor film is formed, forming a dielectric interfacial layer in the opening and contacting the exposed top surface of the semiconductor region;
in a deposition process, selectively depositing a high-k dielectric layer over and contacting the dielectric interfacial layer, wherein the selective depositing the high-k dielectric layer is performed using a hafnium-containing process gas, wherein the high-k dielectric layer, as deposited, is free from portions on the sidewalls of the gate spacers, and is free from portions over the gate spacers;
after the high-k dielectric layer is deposited, removing an upper portion of the inhibitor film, wherein a bottom portion of the inhibitor film remains after the removing; and
forming a replacement gate electrode in a remaining portion of the opening that remains after the deposition process.
8 . The method of claim 7 , wherein the dielectric interfacial layer is formed when the inhibitor film is on the gate spacers.
9 . A method comprising:
removing a dummy gate stack to form an opening between gate spacers, wherein a surface of a semiconductor region is exposed to the opening as an exposed top surface of the semiconductor region;
selectively forming an inhibitor film on exposed dielectric features, wherein the semiconductor region prohibits the inhibitor film to form thereon;
forming a dielectric interfacial layer in the opening and contacting the exposed top surface of the semiconductor region;
in a deposition process, selectively depositing a high-k dielectric layer over and contacting the dielectric interfacial layer, wherein the high-k dielectric layer is selectively deposited by using the inhibitor film to prevent the high-k dielectric layer from grown on the gate spacers, and wherein the high-k dielectric layer, as deposited, is free from portions on sidewalls of the gate spacers, and is free from portions over the gate spacers;
removing the inhibitor film, wherein after the removing, a residue portion of the inhibitor film remains; and
forming a replacement gate electrode in a remaining portion of the opening that remains after the deposition process, wherein the replacement gate electrode contacts the gate spacers to form vertical interfaces.
10 . The method of claim 9 , wherein the dielectric interfacial layer is formed after the inhibitor film is formed.
11 . The method of claim 9 , wherein the forming the replacement gate electrode comprises:
depositing a plurality of conductive materials; and
performing a planarization process on the plurality of conductive materials, wherein at a time after the planarization process, the vertical interfaces have top ends at a same level as top ends of the gate spacers.
12 . The method of claim 7 , wherein the replacement gate electrode seals a void left by the inhibitor film that has been removed.
13 . The method of claim 9 , wherein the replacement gate electrode seals a void left by the inhibitor film that has been removed.
14 . The method of claim 1 , wherein the forming the inhibitor film comprises a soaking process using a chemical solution comprising a gas dissolved in a solvent, and wherein the gas comprises a Si—Cl based process gas or a Si—N based process gas.
15 . The method of claim 4 , wherein in the thermal treatment process, the inhibitor film is decomposed.
16 . The method of claim 7 , wherein the forming the inhibitor film comprises a soaking process using a chemical solution that comprises a gas dissolved in a solvent, and wherein the gas comprises a Si—Cl based process gas or a Si—N based process gas.
17 . The method of claim 7 , wherein the removing the upper portion of the inhibitor film comprises a heating process to decompose the inhibitor film.
18 . The method of claim 9 , wherein the selectively forming the inhibitor film comprises a soaking process using a chemical solution that comprises a gas dissolved in a solvent, and wherein the gas comprises a Si—Cl based process gas or a Si—N based process gas.
19 . The method of claim 9 , wherein the removing the inhibitor film comprises a heating process to decompose the inhibitor film.
20 . The method of claim 1 , wherein the removing the portion of the inhibitor film comprises an etching process.