IP Library › Granted Patent US 12684851

Granted Patent B2

US 12684851 · App. 17/896,353 · Granted Jul 14, 2026

Semiconductor structure

Inventors: Meng-Yu Lin (New Taipei City, TW); Chun-Fu Cheng (Zhubei City, TW); Hsiang-Hung Huang (Taipei City, TW)

Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

H10D64/258 H10D30/014 H10D30/43 H10D30/6729 H10D30/6735 H10D30/6757 H10D62/121 H10D62/151 H10D64/01 H10D84/0167 H10D84/017 H10D84/0186 H10D84/038 H10D84/85 H10B10/125

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Quick Facts

Patent No.: US 12684851
App. No.: 17/896,353
Granted: Jul 14, 2026
Kind: B2

External Links

USPTO Patent Center↗ Full Patent PDF↗

Abstract

A semiconductor structure includes a first transistor, a second transistor, a metal rail, and a first source/drain contact and a second source/drain contact. The first transistor has a gate structure, a first source/drain feature, and a second source/drain feature. The first source/drain feature and the second source/drain feature are on opposite sides of the gate structure. The second transistor has the gate structure, a third source/drain feature directly over the first source/drain feature, and a fourth source/drain feature directly over the second source/drain feature. The metal rail extends in an X-direction and adjacent to the gate structure in a Y-direction. The first source/drain contact and the second source/drain contact each has an L-shape in a Y-Z cross-sectional view. The first source/drain contact electrically connects the first source/drain feature to the metal rail. The second source/drain contact electrically connects the fourth source/drain feature to the metal rail.

Claims (48)

1 . A semiconductor structure, comprising:

a first transistor having a gate structure, a first source/drain feature, and a second source/drain feature, wherein the first source/drain feature and the second source/drain feature are on opposite sides of the gate structure;

a second transistor having the gate structure, a third source/drain feature directly over the first source/drain feature, and a fourth source/drain feature directly over the second source/drain feature;

a metal rail extending in an X-direction and adjacent to the gate structure in a Y-direction; and

a first source/drain contact and a second source/drain contact each having an L-shape in a Y-Z cross-sectional view, wherein the first source/drain contact electrically connects the first source/drain feature to the metal rail, wherein the second source/drain contact electrically connects the fourth source/drain feature to the metal rail.

2 . The semiconductor structure of claim 1 , wherein a top surface of the metal rail is lower than bottom surfaces of the third source/drain feature and the fourth source/drain feature.

3 . The semiconductor structure of claim 1 , further comprising:

contact etch stop layers on sidewalls of the first source/drain feature and the fourth source/drain feature to respectively separate the first source/drain contact and the second source/drain contact from the sidewalls of the first source/drain feature and the fourth source/drain feature.

4 . The semiconductor structure of claim 1 , wherein the first source/drain contact and the second source/drain contact are respectively in contact with sidewalls of the first source/drain feature and the fourth source/drain feature.

5 . The semiconductor structure of claim 1 , wherein the first source/drain contact and the second source/drain contact each comprises:

an extension portion in contact with a sidewall of the metal rail.

6 . The semiconductor structure of claim 1 , further comprising:

a sidewall layer between the gate structure and the metal rail in the Y-direction.

7 . The semiconductor structure of claim 6 , wherein a width of the sidewall layer in the Y-direction is in a range from 5 nm to 20 nm.

8 . The semiconductor structure of claim 1 , further comprising:

a dielectric layer adjacent to the gate structure in the Y-direction, wherein a top surface of the dielectric layer is in contact with a bottom surface of the metal rail and higher than top surfaces of the first source/drain feature and the second source/drain feature.

9 . The semiconductor structure of claim 1 , wherein a thickness of the metal rail is in a range from 10 nm to 50 nm.

10 . A semiconductor structure, comprising:

first nanostructures stacked over each other in a Z-direction;

second nanostructures directly over the first nanostructures and stacked over each other in the Z-direction;

a gate structure wrapping around the first nanostructures and the second nanostructures;

a first source/drain feature connected to the first nanostructures;

a second source/drain feature connected to the second nanostructures, wherein the first source/drain feature and the second source/drain feature are on opposite sides of the gate structure;

a metal rail extending in an X-direction and adjacent to the gate structure in a Y-direction; and

11 . The semiconductor structure of claim 10 , further comprising:

a dielectric layer between the first nanostructures and the second nanostructures, wherein the dielectric layer is thicker than the first nanostructures and the second nanostructures.

12 . The semiconductor structure of claim 10 , wherein a bottom surface of the metal rail is higher than a topmost surface of the first nanostructures, and a top surface of the metal rail is lower than a bottommost surface of the second nanostructures.

13 . The semiconductor structure of claim 10 , wherein the first source/drain contact and the second source/drain contact are separated from sidewalls of the first source/drain feature and the second source/drain feature.

14 . The semiconductor structure of claim 10 , further comprising:

two sidewall layers in contact with sidewalls of the metal rail in the Y-direction.

15 . The semiconductor structure of claim 14 , wherein the first source/drain contact and the second source/drain contact are in contact with the two sidewall layers.

16 . The semiconductor structure of claim 10 , wherein a width of the metal rail in the Y-direction is in a range from 10 nm to 40 nm.

17 . A semiconductor structure, comprising:

first nanostructures stacked over each other;

second nanostructures over the first nanostructures and stacked over each other;

a gate structure wrapping around the first nanostructures and the second nanostructures;

a first source/drain feature and a second source/drain feature attached to the first nanostructures in a first direction;

a third source/drain feature and a fourth source/drain feature attached to the second nanostructures in the first direction, wherein the third source/drain feature is over the first source/drain feature and the fourth source/drain feature is over the second source/drain feature;

a metal rail extending in the first direction and adjacent to the gate structure in a second direction perpendicular to the first direction;

a first source/drain contact over the third source/drain feature and the metal rail; and

a second source/drain contact under the second source/drain feature and the metal rail,

wherein the first source/drain contact electrically connects the third source/drain feature to the metal rail,

wherein the second source/drain contact electrically connects the second source/drain feature to the metal rail.

18 . The semiconductor structure of claim 17 , wherein a bottom surface of the metal rail is higher than the first source/drain feature and the second source/drain feature, and a top surface of the metal rail is lower than the third source/drain feature and the fourth source/drain feature.

19 . The semiconductor structure of claim 17 , further comprising:

sidewall layers on opposite sides of the metal rail in the second direction, wherein the first source/drain contact interfaces a top surface of the sidewall layers and the second source/drain contact interfaces a bottom surface of the sidewall layers.

20 . The semiconductor structure of claim 17 , wherein a bottommost surface of the first source/drain contact is lower than a top surface of the metal rail and a topmost surface of the second source/drain contact is higher than a bottom surface of the metal rail.