Interconnect structure having a multi-deck conductive feature and method of forming the same
The present disclosure provides a semiconductor device structure that includes: a fin active region extruded above a semiconductor substrate; a gate stack disposed on the fin active region, wherein the gate stack includes a gate dielectric layer and a gate electrode; source/drain (S/D) features formed on the fin active region and interposed by the gate stack; and a conductive feature electrically connected to the gate electrode or the S/D features. The conductive feature includes a bottom metal feature of a first metal; a top metal feature of a second metal over the bottom metal feature, wherein the second metal is different from the first metal in composition; a barrier layer surrounding both the top metal feature and the bottom metal feature; and a liner surrounding both the top metal feature and separating the top metal feature from the bottom metal feature and the barrier layer.
1 . A semiconductor device structure, comprising:
a fin active region extruded above a semiconductor substrate;
a gate stack disposed on the fin active region, wherein the gate stack includes a gate dielectric layer and a gate electrode;
source/drain (S/D) features formed on the fin active region and interposed by the gate stack; and
a conductive feature electrically connected to one of the S/D features, wherein the conductive feature includes:
a bottom metal feature of a first metal;
a top metal feature of a second metal over the bottom metal feature, wherein the second metal is different from the first metal in composition, and wherein the first metal is cobalt and the second metal is copper;
a barrier layer surrounding both the top metal feature and the bottom metal feature; and
a liner of the first metal surrounding the top metal feature and separating the top metal feature from the bottom metal feature and the barrier layer, wherein the barrier layer and the liner are different in composition.
2 . The semiconductor device structure of claim 1 , wherein the barrier layer includes tantalum nitride.
3 . The semiconductor device structure of claim 1 , wherein the liner includes a bottom surface spanning a first width and the bottom metal feature includes a top surface spanning a second width being equal to the first width, and wherein the bottom surface of the liner is fully aligned with the top surface of the bottom metal feature.
4 . The semiconductor device structure of claim 1 , further comprising a contact feature landing on one of the S/D features, wherein the conductive feature is electrically connected to the contact feature.
5 . The semiconductor device structure of claim 4 , further comprising a via feature landing on the contact feature, wherein the conductive feature is landing on the via feature.
6 . The semiconductor device structure of claim 1 , wherein the second metal has a conductivity greater than that of the first metal.
7 . The semiconductor device structure of claim 1 ,
wherein the conductive feature is embedded within a first interlayer dielectric (ILD) layer having a first etch stop layer and a first low-k dielectric layer over the first etch stop layer,
wherein the barrier layer lands on a top surface of a second ILD layer having a second etch stop layer and a second low-k dielectric layer over the second etch stop layer.
8 . A semiconductor device structure, comprising:
a semiconductor substrate having an active region;
a gate stack disposed on the active region, wherein the gate stack includes a high-k gate dielectric layer and a metal gate electrode;
a source/drain (S/D) feature formed on the active region and disposed on an edge of the gate stack;
a conductive via landing on the metal gate electrode; and
a conductive feature landing on the conductive via and electrically connected to the metal gate electrode, wherein the conductive feature includes:
a bottom metal feature of a first metal that includes cobalt;
a top metal feature of a second metal that includes copper over the bottom metal feature, wherein the second metal is different from the first metal in composition;
a barrier layer directly contacting a bottom surface of the bottom metal feature; and
a liner layer of the first metal that includes cobalt directly contacting a top surface of the bottom metal feature and directly contacting a bottom surface of the top metal feature,
wherein a portion of the liner layer is disposed between the top metal feature and the barrier layer.
9 . The semiconductor device structure of claim 8 , wherein the liner and the barrier layers are different in composition.
10 . The semiconductor device structure of claim 9 , wherein the barrier layer includes tantalum nitride.
11 . The semiconductor device structure of claim 9 , wherein the first metal has a smaller electrical conductivity than the second metal.
12 . The semiconductor device structure of claim 8 ,
wherein the gate stack further includes a capping layer over the high-k gate dielectric layer, a work function layer over the capping layer, and a seed layer over the work function layer, wherein the metal gate electrode is formed over the seed layer.
13 . The semiconductor device structure of claim 8 , wherein the top metal feature as a greater thickness than the bottom metal feature.
14 . A semiconductor device structure, comprising:
a semiconductor substrate having an active region;
a gate stack disposed on the active region, wherein the gate stack includes a gate dielectric layer and a gate electrode;
a source/drain (S/D) feature formed on the active region and disposed on an edge of the gate stack; and
a conductive feature electrically connected to the S/D features, wherein the conductive feature is embedded within a first interlayer dielectric (ILD) layer having a first etch stop layer and a first low-k dielectric layer over the first etch stop layer, the conductive feature includes:
a bottom metal feature of a first metal that includes cobalt;
a top metal feature of a second metal that includes copper over the bottom metal feature, wherein the second metal is different from the first metal in composition;
a barrier layer surrounding both the top metal feature and the bottom metal feature, wherein the barrier layer is in direct contact with the bottom metal feature without directly contacting the top metal feature, wherein the barrier layer lands on a top surface of a second ILD layer having a second etch stop layer and a second low-k dielectric layer over the second etch stop layer; and
a liner of the first metal that includes cobalt surrounding the top metal feature, wherein the barrier layer surrounds the liner and the bottom metal feature, wherein the barrier layer and the liner are different in composition.
15 . The semiconductor device structure of claim 14 , wherein a conductivity of the second metal is greater than that of the first metal.
16 . The semiconductor device structure of claim 14 , wherein the barrier layer includes tantalum nitride.
17 . The semiconductor device structure of claim 14 , wherein the liner includes a bottom surface spanning a first width and the bottom metal feature includes a top surface spanning a second width being equal to the first width, and wherein the bottom surface of the liner is fully aligned with the top surface of the bottom metal feature.
18 . The semiconductor device structure of claim 14 , wherein
the bottom metal feature has a thickness ranging between 5 nm and 450 nm;
the top metal feature has a thickness ranging between 5 nm and 450 nm;
the liner has a thickness ranging between 0.5 nm and 5 nm; and
the conductive feature has a width ranging between 5 nm and 400 nm.
19 . The semiconductor device structure of claim 14 , wherein
the top metal feature has a thickness Tt;
the bottom metal feature has a thickness Tb; and
a ratio of Tb/Tt ranges between 0.5 and 1.5.
20 . The semiconductor device structure of claim 14 , further comprising:
silicide features on the S/D features; and
a metal contact on the silicide features, wherein the conductive feature lands on the metal contact, and the metal contact includes a barrier layer, a seed layer, and a fill layer, wherein the seed layer surrounds outer surfaces of the fill layer, and the barrier layer surrounds outer surfaces of the seed layer.