Semiconductor structure comprising air spacer on sidewalls of gate electrode layer and fabrication method thereof
A semiconductor structure and its fabrication method are provided. The semiconductor structure includes: a substrate including a base substrate, fins, and an isolation structure; a first dielectric layer; gate structures in the first dielectric layer, where each gate structure includes a gate electrode layer and a gate dielectric layer; air spacers and second spacers on sidewalls of gate electrode layers, where the air spacers are located between the gate electrode layers and the second spacers to expose the sidewalls of the gate electrode layers and the second spacers; source/drain layers in the fins at sides of each gate structure; first conductive structures in the first dielectric layer and on the source/drain layers; and a second dielectric layer on the first dielectric layer and the gate structures, located on the air spacers. The air spacers are also located between the first conductive structures and the gate electrode layers.
1 . A semiconductor structure, comprising:
a substrate;
a gate structure over the substrate, wherein the gate structure includes a gate electrode layer and a gate dielectric layer under the gate electrode layer,
on each side of the gate electrode layer, a protective layer is sandwiched between a sidewall spacer and the gate dielectric layer along a lateral direction;
a first air spacer, over each of the protective layer and a portion of the gate dielectric layer and between the sidewall spacer and the gate electrode layer, wherein the sidewall spacer, the protective layer, and the gate dielectric layer are made of different materials, and tops of the protective layer and the gate dielectric layer are coplanar with each other;
a source layer and a drain layer, in the substrate and on each side of the gate structure; and
a first conductive structure over each of the source layer and the drain layer, wherein the sidewall spacer is formed on a sidewall of the first conductive structure.
2 . The semiconductor structure according to claim 1 , wherein:
the gate dielectric layer includes a portion on a lower portion of sidewalls of the gate electrode layer.
3 . The semiconductor structure according to claim 1 ,
wherein:
bottoms of the sidewall spacer, the protective layer, and the gate dielectric layer are coplanar with each other over the substrate.
4 . The semiconductor structure according to claim 1 , wherein:
the first conductive structure is formed on an entire surface of each of the source layer and the drain layer.
5 . The semiconductor structure according to claim 1 , further comprising:
a second conductive structure over the first conductive structure,
a third conductive structure over the gate electrode layer,
a dielectric layer above the sidewall spacer and the first air spacer on each side of the gate electrode layer, and
a second air spacer contained in the dielectric layer, and between the second and third conductive structures on each side of the gate electrode layer.
6 . The semiconductor structure according to claim 5 , wherein:
the second conductive structure is formed over an entire surface of the first conductive structure, and
the third conductive structure is formed over an entire surface of the gate electrode layer.
7 . The semiconductor structure according to claim 1 , wherein:
the protective layer is made of a material including silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, silicon oxycarbonitride, or a combination thereof.
8 . The semiconductor structure according to claim 1 , wherein:
the gate dielectric layer is made of a high-K dielectric material.
9 . The semiconductor structure according to claim 1 , wherein:
a depth-to-width ratio of the first air spacer is about 2:1 to about 10:1.
10 . A fabrication method of a semiconductor structure, comprising:
providing a substrate;
forming a gate structure over the substrate, wherein the gate structure includes a gate electrode layer and a gate dielectric layer under the gate electrode layer,
on each side of the gate electrode layer, forming a protective layer that is sandwiched between a sidewall spacer and the gate dielectric layer along a lateral direction, wherein
a first air spacer is formed over each of the protective layer and a portion of the gate dielectric layer and between the sidewall spacer and the gate electrode layer, and the sidewall spacer, the protective layer, and the gate dielectric layer are made of different materials, and wherein tops of the protective layer and the gate dielectric layer are coplanar with each other;
forming a source layer and a drain layer in the substrate and on each side of the gate structure; and
forming a first conductive structure over each of the source layer and the drain layer, wherein the sidewall spacer is formed on a sidewall of the first conductive structure.
11 . The fabrication method according to claim 10 , wherein:
bottoms of the sidewall spacer, the protective layer, and the gate dielectric layer are coplanar with each other over the substrate.
12 . The fabrication method according to claim 10 , wherein:
the first conductive structure is formed on an entire surface of each of the source layer and the drain layer.
13 . The fabrication method according to claim 10 , further comprising:
forming a second conductive structure over the first conductive structure,
forming a third conductive structure over the gate electrode layer,
forming a dielectric layer above the sidewall spacer and the first air spacer on each side of the gate electrode layer, wherein
a second air spacer contained in the dielectric layer, and between the second and third conductive structures on each side of the gate electrode layer.
14 . The fabrication method according to claim 13 ,
wherein:
the second conductive structure is formed over an entire surface of the first conductive structure, and
the third conductive structure is formed over an entire surface of the gate electrode layer.
15 . The fabrication method according to claim 10 , wherein:
the protective layer is made of a material including silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, silicon oxycarbonitride, or a combination thereof.
16 . The fabrication method according to claim 10 , wherein:
the gate dielectric layer is made of a high-K dielectric material.
17 . The fabrication method according to claim 10 , wherein:
a depth-to-width ratio of the first air spacer is about 2:1 to about 10:1.