Semiconductor structure and fabrication method thereof

1 . A semiconductor structure, comprising:

a substrate;

a first isolation layer in the substrate;

a plurality of composite layers over the substrate, each composite layer including a plurality of channel layers extending along a first direction parallel to the substrate and overlapping along a second direction perpendicular to the substrate, an insulating wall isolating two parts of each channel layer electrically, and a first gate electrode between adjacent channel layers; and

a second isolation layer between adjacent composite layers, the second isolation layer penetrating into the first isolation layer,

wherein the insulating wall includes a part that is above an uppermost channel layer and overlaps the uppermost channel layer in the second direction.

2 . The structure according to claim 1 , wherein the first gate electrode surrounds a side of one of the plurality of channel layers in a plane parallel to the substrate.

3 . The structure according to claim 1 , wherein:

the first gate electrode further includes a portion formed on both sides of an upper portion of the insulating wall; and

the structure further comprises a second gate electrode beside the portion of the first gate electrode and contacting the portion of the first gate electrode.

4 . The structure according to claim 1 , wherein the insulating wall penetrates through the substrate.

5 . The structure according to claim 1 , wherein the substrate includes a plurality of protruding portions, the first isolation layer being between two of the plurality of protruding portions.

6 . The structure according to claim 1 , wherein the insulating wall includes a part that is below a lowest channel layer and overlaps the lowest channel layer in the second direction.

7 . A method for making a semiconductor structure, comprising:

providing a substrate;

forming a first isolation layer in the substrate;

forming a plurality of composite layers over the substrate, each composite layer including a plurality of channel layers extending along a first direction parallel to the substrate and overlapping along a second direction perpendicular to the substrate, an insulating wall isolating two parts of each channel layer electrically, and a first gate electrode between adjacent channel layers; and

forming a second isolation layer between adjacent composite layers, the second isolation layer penetrating into the first isolation layer,

wherein the insulating wall includes a part that is above an uppermost channel layer and overlaps the uppermost channel layer in the second direction.

8 . The method according to claim 7 , further comprising:

forming a part of the insulating wall that is above an uppermost channel layer and overlaps the uppermost channel layer.

9 . The method according to claim 7 , further comprising:

forming a part of the insulating wall that is below a lowest channel layer and overlaps the lowest channel layer.

10 . A semiconductor structure, comprising:

a plurality of composite layers, each composite layer including a plurality of channel layers extending along a first direction and overlapping along a second direction, an insulating wall isolating two parts of each channel layer electrically, and a gate electrode between adjacent channel layers, wherein the first and second directions are perpendicular to each other, and the gate electrode surrounds a side of each channel layer in a plane perpendicular to the second direction,

wherein the insulating wall includes a part that is below a lowest channel layer and overlaps the lowest channel layer in the second direction.

11 . The structure according to claim 10 , further comprising:

a substrate, the plurality of composite layers formed over the substrate;

a first isolation layer in the substrate; and

a second isolation layer between adjacent composite layers, the second isolation layer penetrating into the first isolation layer.

12 . The structure according to claim 11 , wherein the insulating wall penetrates through the substrate.

13 . The structure according to claim 10 , wherein the insulating wall includes a part that is above an uppermost channel layer and overlaps the uppermost channel layer in the second direction.

14 . The structure according to claim 1 , wherein the part that is above the uppermost channel layer and overlaps the uppermost channel layer has a vertical sidewall coplanar with a corresponding vertical sidewall of the uppermost channel layer.

15 . The structure according to claim 10 , wherein the part that is below the lowest channel layer and overlaps the lowest channel layer has a vertical sidewall coplanar with a corresponding vertical sidewall of the lowest channel layer.

16 . The structure according to claim 1 , wherein the first gate electrode includes a metal material including tungsten (W), copper (Cu), and/or gold (Au).

17 . The structure according to claim 1 , further comprising a protective layer sandwiched between the first gate electrode and the second isolation layer.

18 . The structure according to claim 17 , wherein the protective layer includes a dielectric material including one of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, and silicon oxycarbonitride or a combination thereof.

19 . The structure according to claim 3 , wherein a topmost surface of the second gate electrode is flush with a topmost surface of the first gate electrode.

20 . The structure according to claim 1 , wherein the second isolation layer includes a part that is above an uppermost channel layer and overlaps the uppermost channel layer in the second direction.