IP Library Granted Patent US 12684859
Granted Patent B2
US 12684859 · App. 18/465,996 · Granted Jul 14, 2026

Method of forming semiconductor device including semiconductor liner

Inventors: Bong Seok Jeon (Gyeonggi-do, KR); Ji Yong Kim (Gyeonggi-do, KR); Hai Won Kim (Gyeonggi-do, KR); Jeong Hyun Lee (Gyeonggi-do, KR)
Assignee: SK hynix Inc.
H10D84/038H10B12/033H10B12/0335H10B12/05H10B12/053H10B12/482H10D84/0149H10D84/0151H10D84/83H10W10/014H10W10/17
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Quick Facts
Patent No.
US 12684859
App. No.
18/465,996
Granted
Jul 14, 2026
Kind
B2
Abstract

A method for forming a semiconductor device may include forming, on a substrate, a trench which delimits a preliminary active region. A buffer layer may be formed on the preliminary active region using a first heat treatment process that is performed at 520° C. to 580° C. A sacrificial layer may be formed by replacing the buffer layer. An active region may be exposed by removing the sacrificial layer. A semiconductor liner may be formed on the active region.

Claims (47)

1 . A method for forming a semiconductor device, comprising:

forming, on a substrate, a trench which delimits a preliminary active region;

forming a buffer layer on the preliminary active region using a first heat treatment process that is performed at 520° C. to 580° C.;

forming a sacrificial layer on the preliminary active region by replacing the buffer layer;

exposing an active region by removing the sacrificial layer; and

forming a semiconductor liner on the active region.

2 . The method according to claim 1 , wherein the first heat treatment process includes supplying a gas or radicals containing N and O onto the preliminary active region.

3 . The method according to claim 1 , wherein the first heat treatment process includes supplying nitrogen gas and oxygen gas onto the preliminary active region, and the oxygen gas is supplied at a flow rate ranging from 0.1 SLM (standard liter per minute) to 1 SLM.

4 . The method according to claim 1 , wherein a thickness of the buffer layer ranges from 0.1 nm to 1 nm.

5 . The method according to claim 1 , wherein the buffer layer includes at least one or more of silicon oxide, silicon nitride or silicon oxynitride.

6 . The method according to claim 1 , wherein the forming of the sacrificial layer by replacing the buffer layer comprises:

supplying a reactive gas such as a nitrogen-containing gas, a fluorine-containing gas, a hydrogen-containing gas or a combination thereof onto the substrate with the buffer layer.

7 . The method according to claim 1 , wherein the forming of the sacrificial layer by replacing the buffer layer comprises:

supplying nitrogen trifluoride (NF 3 ) gas, ammonia (NH 3 ) gas, hydrogen (H 2 ) gas and argon (Ar) gas onto the substrate with the buffer layer.

8 . The method according to claim 1 , wherein the sacrificial layer includes ammonium fluorosilicate ((NH 4 ) 2 [SiF 6 ]).

9 . The method according to claim 1 , wherein the exposing of the active region by removing the sacrificial layer includes a second heat treatment process that is performed at a temperature of 80° C. to 150° C.

10 . The method according to claim 9 , wherein the second heat treatment process is performed in a chamber to which nitrogen (N 2 ) gas is supplied.

11 . The method according to claim 1 , wherein the preliminary active region has a first width, the active region has a second width, and the second width is smaller than the first width by 0.5 nm to 1.1 nm.

12 . The method according to claim 1 , wherein the forming of the semiconductor liner on the active region includes a selective epitaxial growth (SEG) process or a selective poly growth (SPG) process.

13 . The method according to claim 1 , wherein the semiconductor liner includes monocrystalline silicon, polysilicon or a combination thereof.

14 . The method according to claim 1 , wherein a thickness of the semiconductor liner ranges from 1 nm to 4 nm.

15 . A method for forming a semiconductor device, comprising:

forming, on a substrate, an isolation layer which delimits an active pattern;

forming a word line which traverses the active pattern;

forming a plurality of source/drain regions in the active pattern adjacent to the word line;

forming a bit line which is connected to one of the plurality of source/drain regions;

forming a bottom electrode which is connected to another one of the plurality of source/drain regions;

forming a capacitor dielectric layer on the bottom electrode; and

forming a top electrode on the capacitor dielectric layer,

wherein the forming of the isolation layer comprises:

forming, on the substrate, a trench which delimits a preliminary active region;

forming a buffer layer on the preliminary active region using a first heat treatment process that is performed at 520° C. to 580° C.;

forming a sacrificial layer by replacing the buffer layer;

exposing an active region by removing the sacrificial layer;

forming a semiconductor liner on the active region, the active region and the semiconductor liner configuring the active pattern; and

forming the isolation layer in the trench.

16 . A method for forming a semiconductor liner for accommodating a semiconductor device, comprising:

forming, on a substrate, a trench which delimits a preliminary active region;

forming a buffer layer on the preliminary active region using a first heat treatment process which consumes material of the preliminary active region, and thereby forms for the semiconductor liner a device region having a first width smaller than a second width of the preliminary active region prior to the first treatment;

forming a sacrificial layer by replacing the buffer layer;

removing the sacrificial layer and thereby exposing the device region; and

forming the semiconductor device on the device region.

17 . The method of claim 16 , wherein the first width of the device region is smaller than the second width of the preliminary active region by 0.5 nm to 1.1 nm.

18 . The method of claim 16 , wherein

the device region comprises a strip of a semiconductor wafer, and

after removing the sacrificial layer, the first width of the device region is substantial enough so that the device region does not lean.

19 . The method of claim 18 , wherein the first width of the device region ranges from 10 to 30 nm.