Semiconductor structure and method for forming the same
A semiconductor structure includes a first dielectric wall over a substrate, and two metal gate structures disposed at two sides of the first dielectric wall. Each of the metal gate structures includes a plurality of nanosheets stacked over the substrate and separated from each other, a high-k gate dielectric layer covering each of the nanosheets, and a metal layer covering and over the plurality of nanosheets and the high-k gate dielectric layer. The high-k gate dielectric layer of each metal gate structure is disposed between the metal layer of each metal gate structure and the first dielectric wall.
1 . A method for forming a semiconductor structure, comprising:
forming a nanosheet stack over a substrate, wherein the nanosheet stack comprises a plurality of nanosheets extending in a first direction;
forming a sacrificial gate structure over the nanosheet stack and extending in a second direction;
removing a portion of the sacrificial gate structure to form a first trench extending in the first direction;
forming a first dielectric wall in the first trench;
removing a remaining portion of the sacrificial gate structure to form a plurality of second trenches extending in the second direction, wherein the nanosheet stack is exposed through the second trenches;
removing portions of the nanosheet stack to form a plurality of nanosheets separated from each other;
forming a high-k gate dielectric layer and a first metal layer in the second trenches;
forming a second dielectric wall in the second trenches; and
forming a second metal layer over the second dielectric wall.
2 . The method of claim 1 , further comprising:
forming a third metal layer to fill spaces between the nanosheets and cover the high-k gate dielectric layer; and
removing a portion of the third metal layer to exposed a portion of the high-k gate dielectric layer.
3 . The method of claim 1 , wherein the high-k gate dielectric layer and the first metal layer cover portions of sidewalls and a top surface of the first dielectric wall.
4 . The method of claim 1 , further comprising:
forming a protection structure over the first dielectric wall, the nanosheets, a portion of the first metal layer and a portion of the high-k gate dielectric layer;
removing a portion of the first metal layer exposed through the protection structure and a portion of the high-k gate dielectric layer exposed through the protection structure; and
removing the protection structure.
5 . The method of claim 1 , wherein the forming of the second dielectric wall further comprises:
forming a first dielectric layer and a second dielectric layer over the first dielectric wall and the nanosheets; and
removing a portion of the first dielectric layer and a portion of the second dielectric layer such that a top surface of the first dielectric layer and a top surface of the second dielectric layer are level with or lower than a top surface of a topmost nanosheet.
6 . The method of claim 5 , further comprising forming a third dielectric wall to separate the second dielectric layer and penetrate the second dielectric wall.
7 . A method for forming a semiconductor structure, comprising:
forming a nanosheet stack extending in a first direction;
forming a sacrificial gate structure over the nanosheet stack and extending in a second direction;
replacing a portion of the sacrificial gate structure with a first dielectric wall, wherein the first dielectric wall extends in the first direction;
removing a remaining portion of the sacrificial gate structure to form a plurality of first trenches extending in the second direction, wherein the nanosheet stack is exposed through the first trenches;
removing portions of the nanosheet stack to form a plurality of nanosheets separated from each other;
forming a high-k gate dielectric layer and a first metal layer in the first trenches;
forming a second dielectric wall in the first trenches; and
forming a second metal layer over the second dielectric wall,
wherein a top surface of the second metal layer is aligned with a top surface of the first dielectric wall.
8 . The method of claim 7 , wherein the replacement of the portion of the sacrificial gate structure with the first dielectric wall comprises:
removing the portion of the sacrificial gate structure to form a second trench extending in the first direction; and
forming the first dielectric wall in the second trench.
9 . The method of claim 8 , wherein formation of the first dielectric wall further comprises:
forming a first dielectric layer to line a bottom and sidewalls of the second trench; and
forming a second dielectric layer to fill the second trench.
10 . The method of claim 9 , wherein a thickness of the first dielectric layer is less than a thickness of the second dielectric layer.
11 . The method of claim 9 , further comprising removing a portion of the first dielectric layer such that a portion of sidewalls of the second dielectric layer is exposed through the first trench.
12 . The method of claim 9 , further comprising a liner disposed between the first dielectric layer and the nanosheet stack.
13 . The method of claim 9 , further comprising removing portions of the first dielectric layer after the formation of the plurality of nanosheets.
14 . The method of claim 7 , wherein the high-k gate dielectric layer covers sidewalls of the first dielectric wall.
15 . The method of claim 7 , further comprising forming a third dielectric wall in the second metal layer and the second dielectric wall, wherein a top surface of the third dielectric wall is aligned with the top surface of the first dielectric wall and the top surface of the second metal layer.
16 . A method for forming a semiconductor structure, comprising:
forming a nanosheet stack extending in a first direction;
forming a sacrificial gate structure over the nanosheet stack and extending in a second direction;
replacing a portion of the sacrificial gate structure with a first dielectric wall, wherein the first dielectric wall extends in the first direction;
removing a remaining portion of the sacrificial gate structure to form a plurality of first trenches extending in the second direction, wherein the nanosheet stack is exposed through the first trenches;
removing portions of the nanosheet stack to form a plurality of nanosheets separated from each other;
forming a high-k gate dielectric layer and a first metal layer in the first trenches;
forming a first dielectric layer and a second dielectric layer over the first dielectric wall and the nanosheets; and
removing a portion of the first dielectric layer and a portion of the second dielectric layer to form a second dielectric wall, wherein a top surface of the second dielectric wall is lower than a top surface of the first dielectric wall.
17 . The method of claim 16 , wherein the top surface of the second dielectric wall is level with or lower than a top surface of a topmost nanosheet.
18 . The method of claim 16 , further comprising forming a second metal layer over the top surface of the second dielectric wall.
19 . The method of claim 18 , wherein a top surface of the second metal layer is aligned with the top surface of the first dielectric wall.
20 . The method of claim 16 , further comprising forming a third dielectric wall to separate the second dielectric layer and penetrate the second dielectric wall.