IP Library › Granted Patent US 12684863
Granted Patent B2
US 12684863 · App. 17/939,392 · Granted Jul 14, 2026

Folded series switches

Inventors: Thomas Hua-Min Williams (Irvine, CA); Conor Roche (Cork, IE); Khaja Ahmad Shaik (San Diego, CA); Hanil Lee (San Diego, CA); Roger Lee Mills (Pflugerville, TX); Benjamin Griffitts (Santa Ana, CA)
Assignee: QUALCOMM INCORPORATED
H10D84/834H10D64/519H10W20/43
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Quick Facts
Patent No.
US 12684863
App. No.
17/939,392
Granted
Jul 14, 2026
Kind
B2
Abstract

A chip includes a first active region, first gates extending over the first active region in a first direction, wherein the first gates correspond to a first transistor, and second gates extending over the first active region in the first direction, wherein the second gates correspond to a second transistor.

Claims (57)

1 . A chip, comprising:

a first active region;

first gates extending over the first active region in a first direction, wherein the first gates correspond to a first transistor;

second gates extending over the first active region in the first direction, wherein the second gates correspond to a second transistor, a first one of the first gates and a second one of the first gates are between a first one of the second gates and a second one of the second gates, the first transistor and the second transistor share a first source/drain in the first active region between the first one of the first gates and the first one of the second gates, and the first transistor and the second transistor share a second source/drain in the first active region between the second one of the first gates and the second one of the second gates;

a first gate interconnect coupling the first gates to one another;

a second gate interconnect coupling the second gates to one another;

a second active region;

third gates extending over the second active region in the first direction, wherein the third gates correspond to a third transistor;

a first metal routing coupling the first source/drain in the first active region to a first source/drain in the second active region; and

a second metal routing coupling the second source/drain in the first active region to a second source/drain in the second active region.

2 . The chip of claim 1 , wherein:

a number of the first gates is even; and

a number of the second gates is even.

3 . The chip of claim 2 , wherein a ratio of the number of the first gates to the number of the second gates is 2:2.

4 . The chip of claim 1 , wherein the first gates are interspersed across the first active region.

5 . The chip of claim 4 , wherein the second gates are interspersed across the second active region.

6 . The chip of claim 1 , wherein:

the first active region includes fins extending in a second direction that is perpendicular to the first direction;

the first gates are formed over the fins; and

the second gates are formed over the fins.

7 . The chip of claim 1 , wherein a number of the third gates is equal to a sum of a number of the first gates and a number of the second gates.

8 . The chip of claim 7 , wherein:

a number of the first gates is even; and

a number of the second gates is even.

9 . The chip of claim 1 , further comprising

a third gate interconnect coupling the third gates to one another.

10 . A chip, comprising:

a first active region;

first gates extending over the first active region in a first direction, wherein the first gates correspond to a first transistor;

second gates extending over the first active region in the first direction, wherein the second gates correspond to a second transistor, a first one of the first gates and a second one of the first gates are between a first one of the second gates and a second one of the second gates, the first transistor and the second transistor share a first source/drain in the first active region between the first one of the first gates and the first one of the second gates, and the first transistor and the second transistor share a second source/drain in the first active region between the second one of the first gates and the second one of the second gates;

a second active region;

third gates extending over the second active region in the first direction, wherein the third gates correspond to a third transistor;

a first metal routing coupling the first source/drain in the first active region to a first source/drain in the second active region;

a second metal routing coupling the second source/drain in the first active region to a second source/drain in the second active region; and

a switch having a first terminal and a second terminal, wherein the first terminal is coupled to the third gates and the second terminal is coupled to the first source/drain in the first active region.

11 . The chip of claim 1 , further comprising a first supply rail coupled to a third source/drain in the first active region.

12 . The chip of claim 11 , wherein the third source/drain is between the first one of the first gates and the second one of the first gates.

13 . The chip of claim 12 , further comprising:

a third metal routing coupling a fourth source/drain in the first active region to a third source/drain in the second active region, wherein the first one of the second gates is between the fourth source/drain in the first active region and the first source/drain in the first active region; and

a fourth metal routing coupling a fifth source/drain in the first active region to a fourth source/drain in the second active region, wherein the second one of the second gates is between the fifth source/drain in the first active region and the second source/drain in the first active region.

14 . The chip of claim 13 , further comprising

a second supply rail coupled to the fourth source/drain in the first active region and the fifth source/drain in the first active region.

15 . The chip of claim 13 , wherein a first one of the third gates is between the third source/drain in the second active region and the first source/drain in the second active region, and a second one of the third gates is between the second source/drain in the second active region and the fourth source/drain in the second active region.

16 . The chip of claim 13 , further comprising a switch having a first terminal and a second terminal, wherein the first terminal is coupled to the second gates and the second terminal is coupled to the fourth source/drain in the first active region and the fifth source/drain in the first active region.

17 . The chip of claim 13 , wherein the first source/drain in the first active region is configured to act as a drain for the first transistor and a source for the second transistor.

18 . A chip, comprising:

a first active region;

first gates extending over the first active region in a first direction, wherein the first gates correspond to a first transistor;

second gates extending over the first active region in the first direction, wherein the second gates correspond to a second transistor, a first one of the first gates and a second one of the first gates are between a first one of the second gates and a second one of the second gates, the first transistor and the second transistor share a first source/drain in the first active region between the first one of the first gates and the first one of the second gates, and the first transistor and the second transistor share a second source/drain in the first active region between the second one of the first gates and the second one of the second gates;

a second active region;

third gates extending over the second active region in the first direction, wherein the third gates correspond to a third transistor, the first transistor and the second transistor are of a same channel type, and the third transistor is of a different channel type than the first transistor and the second transistor;

a first metal routing coupling the first source/drain in the first active region to a first source/drain in the second active region; and

a second metal routing coupling the second source/drain in the first active region to a second source/drain in the second active region.

19 . The chip of claim 18 , wherein:

the first transistor includes a first p-type transistor;

the second transistor includes a second p-type transistor; and

the third transistor includes an n-type transistor.