IP Library › Granted Patent US 12684864
Granted Patent B2
US 12684864 · App. 18/165,486 · Granted Jul 14, 2026

Semiconductor device

Inventors: Yoo Ri Sung (Suwon-si, KR); Ju Youn Kim (Suwon-si, KR); Myung Soo Seo (Suwon-si, KR); Ki Hwan Lee (Gyeonggi-do, KR)
Assignee: SAMSUNG ELECTRONICS CO., LTD.
H10D84/85H10D84/0167H10D84/0184H10D84/038
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Quick Facts
Patent No.
US 12684864
App. No.
18/165,486
Granted
Jul 14, 2026
Kind
B2
Abstract

A semiconductor device includes a substrate that includes a first region and a second region, a first active pattern on the first region and that extends in a first horizontal direction, a second active pattern on the second region and that extends in the first horizontal direction, a first etch stop layer on the first active pattern, a second etch stop layer on the second active pattern, a plurality of first nanosheets on the first etch stop layer and that are stacked in a vertical direction and include silicon germanium (SiGe), a plurality of second nanosheets on the second etch stop layer and that are stacked in the vertical direction, a first gate electrode on the first etch stop layer and that extends in a second horizontal direction, and a second gate electrode disposed on the second etch stop layer and that extends in the second horizontal direction.

Claims (64)

1 . A semiconductor device, comprising:

a substrate that includes a first region and a second region defined therein;

a first active pattern disposed on the first region of the substrate and extending in a first horizontal direction;

a second active pattern disposed on the second region of the substrate and extending in the first horizontal direction;

a first etch stop layer disposed on the first active pattern and including an insulating material;

a second etch stop layer disposed on the second active pattern and including an insulating material;

a plurality of first nanosheets disposed on the first etch stop layer, wherein the plurality of first nanosheets are stacked and spaced apart from each other in a vertical direction and include silicon germanium (SiGe);

a plurality of second nanosheets disposed on the second etch stop layer, wherein the plurality of second nanosheets are stacked and spaced apart from each other in the vertical direction;

a first gate electrode disposed on the first etch stop layer and extending in a second horizontal direction that differs from the first horizontal direction, wherein the first gate electrode surrounds the plurality of first nanosheets; and

a second gate electrode disposed on the second etch stop layer and extending in the second horizontal direction, wherein the second gate electrode surrounds the plurality of second nanosheets,

wherein a portion of the first gate electrode is disposed between the first etch stop layer and a lowermost first nanosheet in the vertical direction.

2 . The semiconductor device of claim 1 , wherein the first etch stop layer and the second etch stop layer are disposed at a same vertical level above the substrate.

3 . The semiconductor device of claim 1 , further comprising:

a first source/drain region disposed on the first active pattern and on at least one side surface of the first gate electrode, wherein a bottom surface of the first source/drain region is in contact with the first etch stop layer; and

a second source/drain region disposed on the second active pattern and on at least one side surface of the second gate electrode, wherein a bottom surface of the second source/drain region is in contact with the second etch stop layer.

4 . The semiconductor device of claim 1 , further comprising:

a first source/drain region disposed on the first active pattern and on at least one side surface of the first gate electrode, wherein the first source/drain region extends through the first etch stop layer and contacts the first active pattern; and

a second source/drain region disposed on the second active pattern and on at least one side surface of the second gate electrode, wherein the second source/drain region extends through the second etch stop layer and contacts the second active pattern.

5 . The semiconductor device of claim 1 , wherein the plurality of second nanosheets includes silicon (Si).

6 . The semiconductor device of claim 1 , wherein vertical levels above the substrate of the plurality of second nanosheets differ from vertical levels above the substrate of the plurality of first nanosheets.

7 . The semiconductor device of claim 1 , wherein a lowermost first nanosheet is spaced apart from the first etch stop layer in the vertical direction,

wherein a lowermost second nanosheet is in contact with the second etch stop layer.

8 . The semiconductor device of claim 1 , wherein the plurality of second nanosheets includes silicon germanium (SiGe).

9 . The semiconductor device of claim 1 , wherein the plurality of second nanosheets and the plurality of first nanosheets are disposed at a same vertical level above the substrate.

10 . The semiconductor device of claim 1 , wherein a lowermost first nanosheet is spaced apart from the first etch stop layer in the vertical direction,

wherein a lowermost second nanosheet is spaced apart from the second etch stop layer in the vertical direction.

11 . The semiconductor device of claim 1 , further comprising an inner spacer disposed between adjacent second nanosheets and on a sidewall in the first horizontal direction of the second gate electrode.

12 . The semiconductor device of claim 1 , wherein the first region is a PMOS region, and the second region is an NMOS region.

13 . A semiconductor device, comprising:

a substrate that includes a PMOS region and a NMOS region formed therein;

a first active pattern disposed on the PMOS region of the substrate and extending in a first horizontal direction;

a second active pattern disposed on the NMOS region of the substrate and extending in the first horizontal direction;

a first etch stop layer disposed on the first active pattern and including an insulating material;

a second etch stop layer disposed on the second active pattern and including an insulating material, wherein the first and second etch stop layers have a same vertical level above the substrate;

a plurality of first nanosheets disposed on the first etch stop layer, wherein the plurality of first nanosheets are stacked and spaced apart from each other in a vertical direction and include silicon germanium (SiGe);

a plurality of second nanosheets disposed on the second etch stop layer, wherein the plurality of second nanosheets are stacked and spaced apart from each other in the vertical direction;

a first gate electrode disposed on the first etch stop layer and extending in a second horizontal direction that differs from the first horizontal direction, wherein the first gate electrode surrounds the plurality of first nanosheets;

a first source/drain region disposed on the first active pattern and on at least one side surface of the plurality of first nanosheets, wherein the first source/drain region is in contact with the first etch stop layer; and

a second source/drain region disposed on the second active pattern and on at least one side surface of the plurality of second nanosheets, wherein the second source/drain region is in contact with the second etch stop layer,

wherein a portion of the first gate electrode is disposed between the first etch stop layer and a lowermost first nanosheet in the vertical direction.

14 . The semiconductor device of claim 13 ,

wherein a bottom surface of the first source/drain region is in contact with the first etch stop layer,

wherein a bottom surface of the second source/drain region is in contact with the second etch stop layer.

15 . The semiconductor device of claim 13 , wherein the plurality of second nanosheets includes silicon (Si).

16 . The semiconductor device of claim 13 , wherein vertical levels of the plurality of second nanosheets differ from vertical levels of the plurality of first nanosheets.

17 . The semiconductor device of claim 13 , wherein the plurality of second nanosheets includes silicon germanium (SiGe).

18 . A semiconductor device, comprising:

A substrate that includes a PMOS region and a NMOS region formed therein;

a first active pattern disposed on the PMOS region of the substrate and extending in a first horizontal direction;

a second active pattern disposed on the NMOS region of the substrate and extending in the first horizontal direction;

a first etch stop layer disposed on the first active pattern and including an insulating material;

a second etch stop layer disposed on the second active pattern and including an insulating material, wherein the first and second etch stop layers have a same vertical level above the substrate;

a plurality of first nanosheets disposed on the first etch stop layer, wherein the plurality of first nanosheets are stacked and spaced apart from each other in a vertical direction and includes silicon germanium (SiGe);

a plurality of second nanosheets disposed on the second etch stop layer, wherein the plurality of second nanosheets are stacked and spaced apart from each other in the vertical direction and include silicon (Si), and vertical levels of the plurality of second nanosheets differ from vertical levels of the plurality of first nanosheets;

a first gate electrode disposed on the first etch stop layer and extending in a second horizontal direction that differs from the first horizontal direction, wherein the first gate electrode surrounds the plurality of first nanosheets;

a second gate electrode disposed on the second etch stop layer and extending in the second horizontal direction, wherein the second gate electrode surrounds the plurality of second nanosheets;

a first source/drain region disposed on the first active pattern and on at least one side surface of the first gate electrode, wherein the first source/drain region is in contact with the first etch stop layer; and

a second source/drain region disposed on the second active pattern and on at least one side surface of the second gate electrode, wherein the second source/drain region is in contact with the second etch stop layer,

wherein a portion of the first gate electrode is disposed between the first etch stop layer and a lowermost first nanosheet in the vertical direction.

19 . The semiconductor device of claim 18 , further comprising:

a first gate spacer in contact with an upper surface of an uppermost first nanosheet;

a second gate spacer spaced apart in the vertical direction from an upper surface of an uppermost second nanosheet; and

an inner spacer disposed between the upper surface of the uppermost second nanosheet and the second gate spacer.

20 . The semiconductor device of claim 19 , wherein a portion of the second gate electrode disposed on the upper surface of the uppermost second nanosheet and between opposing portions of the second gate spacer contacts another portion of the second gate electrode disposed on the upper surface of the uppermost second nanosheet and is disposed between opposing portions of the inner spacer.