Semiconductor device
A semiconductor device includes: a chip having a main surface; a trench insulation structure that defines an active region in the main surface; a first conductivity type well region formed in the active region; a second conductivity type first impurity region formed in the well region; a second impurity region formed in the well region and surrounding the first impurity region in a plan view; a gate electrode formed on the well region between the first impurity region and the second impurity region, and surrounding the first impurity region in a plan view; a gate insulating film formed between the gate electrode and the well region; a gate contact portion formed on the trench insulation structure; and a gate connection portion that crosses the second impurity region from a boundary between the trench insulation structure and the active region and connects the gate contact portion and the gate electrode.
1 . A semiconductor device comprising:
a chip having a main surface;
a trench insulation structure that defines an active region in the main surface;
a first conductivity type well region formed in the active region;
a second conductivity type first impurity region formed in the well region;
a second impurity region formed in the well region and surrounding the first impurity region in a plan view;
a gate electrode formed on the well region between the first impurity region and the second impurity region, and surrounding the first impurity region in a plan view;
a gate insulating film formed between the gate electrode and the well region;
a gate contact portion formed on the trench insulation structure; and
a gate connection portion that crosses the second impurity region from a boundary between the trench insulation structure and the active region and connects the gate contact portion and the gate electrode, wherein
in a plan view of the semiconductor device, a width of the gate connection portion is narrower than a width of the gate electrode in a first direction, which is perpendicular to a second direction in which the gate connection portion crosses the second impurity region.
2 . The semiconductor device of claim 1 , wherein the second impurity region includes:
a pair of first portions formed along the first direction and sandwiching the first impurity region in the second direction; and
a pair of second portions formed along the second direction and sandwiching the first impurity region in the first direction.
3 . The semiconductor device of claim 2 , wherein the gate connection portion selectively crosses at least one of the pair of first portions or the pair of second portions to connect the gate contact portion and the gate electrode.
4 . The semiconductor device of claim 2 , wherein the well region includes:
a first channel region formed between the first impurity region and the pair of first portions of the second impurity region and having a channel formed along the second direction; and
a second channel region formed between the first impurity region and the pair of second portions of the second impurity region and having a channel formed along the first direction.
5 . The semiconductor device of claim 4 , wherein a length of the channel in the first channel region and a length of the channel in the second channel region are substantially equal to each other.
6 . The semiconductor device of claim 4 , wherein the first impurity region is formed in an elongated shape in the second direction, and
wherein the gate electrode is formed in a substantially elliptical annular shape elongated in the second direction and surrounding the first impurity region.
7 . The semiconductor device of claim 6 , wherein, in the plan view,
the gate connection portion is formed at a location facing the first impurity region in the second direction, and
the width of the gate connection portion is narrower than a width of the first impurity region in the first direction.
8 . The semiconductor device of claim 7 , wherein the width of the gate connection portion is 0.08 μm or more and 0.3 μm or less.
9 . The semiconductor device of claim 4 , wherein the second impurity region is formed in an endless annular shape in a plan view.
10 . The semiconductor device of claim 1 , wherein, in the plan view,
the width of the gate connection portion is narrower than a width of the gate contact portion in the first direction.
11 . The semiconductor device of claim 10 , wherein the width of the gate connection portion is 0.08 μm or more and 0.3 μm or less.
12 . The semiconductor device of claim 1 , wherein, in the plan view,
the width of the gate connection portion is narrower than a width of the first impurity region in the first direction.
13 . The semiconductor device of claim 1 , wherein the trench insulation structure includes a trench formed in the main surface, an insulator buried in the main surface and exposing an open end portion of the trench, and a recess recessed toward a bottom wall of the trench at an upper end portion of the insulator, and
wherein the gate connection portion is formed to cover the recess.
14 . The semiconductor device of claim 1 , wherein the first impurity region is a source region, and the second impurity region is a drain region.
15 . The semiconductor device of claim 14 , wherein the active region includes a CMOS region for a CMOS transistor, and
wherein the source region and the drain region are parts of the CMOS transistor.