Self-aligned backside interconnect structures
A semiconductor structure includes a first plurality of backside power rail interconnects located within a first cell height region of a substrate. A second plurality of backside power rail interconnects are located within a second cell height region of the substrate. A first isolation region is located between the first cell height region of the substrate and the second cell height region of the substrate. The first isolation region electrically separates the first cell height region and the second cell height region. A second isolation region is located between adjacent power rail interconnects of the first plurality of backside power rail interconnects and between adjacent power rail interconnects of the second plurality of backside power rail interconnects. The second isolation region electrically separates the adjacent power rail interconnects.
1 . A semiconductor structure, comprising:
a first plurality of backside power rail interconnects located within a first cell height region of a substrate;
a second plurality of backside power rail interconnects located within a second cell height region of the substrate;
a first isolation region located between the first cell height region of the substrate and the second cell height region of the substrate, the first isolation region electrically separating the first cell height region and the second cell height region; and
a second isolation region located between adjacent power rail interconnects of the first plurality of backside power rail interconnects and between adjacent power rail interconnects of the second plurality of backside power rail interconnects, the second isolation region electrically separating the adjacent power rail interconnects,
wherein the first plurality of backside power rail interconnects and the second plurality of backside power rail interconnects connect with a plurality of backside power rails, and the plurality of backside power rails form a grid shape separated by the first isolation region and the second isolation region.
2 . The semiconductor structure of claim 1 , wherein the first plurality of backside power rail interconnects and the second plurality of backside power rail interconnects are configured in a grid shaped arrangement.
3 . The semiconductor structure of claim 1 , wherein the first isolation region includes a diffusion break isolation region.
4 . The semiconductor structure of claim 1 , wherein the second isolation region includes a dielectric liner extending from a shallow trench isolation region.
5 . The semiconductor structure of claim 4 , wherein a critical dimension of the dielectric liner is less than a critical dimension of the shallow trench isolation region.
6 . The semiconductor structure of claim 4 , wherein each of the first plurality of backside power rail interconnects and each of the second plurality of backside power rail interconnects are electrically separated at an N2P space by the dielectric liner extending from the shallow trench isolation region.
7 . The semiconductor structure of claim 1 , wherein the first plurality of backside power rail interconnects and the second plurality of backside power rail interconnects are located between a device region and a backside power delivery network.
8 . The semiconductor structure of claim 7 , wherein the backside power delivery network is electrically connected to at least one of the first plurality of backside power rail interconnects and the second plurality of backside power rail interconnects by a backside via.
9 . The semiconductor structure of claim 8 , wherein the device region further includes:
a front-end-of-line level comprising one or more field effect transistors, the front-end-of-line level electrically connected to a back-end-of-line interconnect level located on a first side of the front-end-of-line level by a plurality of metal contacts, the one or more field effect transistors being electrically separated by a shallow trench isolation region.
10 . The semiconductor structure of claim 9 , further comprising:
a carrier wafer in contact with a surface of the back-end-of-line interconnect level opposing the one or more field effect transistors and the plurality of metal contacts.
11 . The semiconductor structure of claim 7 , wherein one or more of the first plurality of backside power rail interconnects and the second plurality of backside power rail interconnects are electrically connected to the device region by a backside metal contact.