Logic circuits including circuits of different heights and related method of fabrication

1 . A logic circuit, comprising:

a first circuit, comprising:

a first diffusion region disposed on a substrate and having a longitudinal axis disposed in a first direction;

a second diffusion region disposed on the substrate and having a longitudinal axis disposed in the first direction;

a plurality of first gates, each having a first longitudinal axis disposed in a second direction substantially orthogonal to the first direction; and

a plurality of first devices, each comprising:

a portion of the first diffusion region;

a portion of the second diffusion region; and

one of the plurality of first gates disposed on the portion of the first diffusion region and on the portion of the second diffusion region; and

a second circuit, disposed adjacent to, in the second direction, the first circuit, the second circuit comprising:

a third diffusion region disposed on the substrate and having a longitudinal axis disposed in the first direction;

a fourth diffusion region disposed on the substrate and having a longitudinal axis disposed in the first direction;

a plurality of second gates, each having a second longitudinal axis disposed in the second direction; and

a plurality of second devices, each comprising:

a portion of the third diffusion region;

a portion of the fourth diffusion region; and

one of the plurality of second gates disposed on the portion of the third diffusion region and on the portion of the fourth diffusion region;

wherein:

each of the third diffusion region, the fourth diffusion region, the first diffusion region, and the second diffusion region comprises a first side and a second side orthogonal to the second direction;

the fourth diffusion region is disposed on the first side of the third diffusion region;

the first diffusion region is disposed on the first side of the second diffusion region; and

a second distance in the second direction from the first side of the fourth diffusion region to the second side of the third diffusion region is less than a first distance in the second direction from the first side of the first diffusion region to the second side of the second diffusion region.

2 . The logic circuit of claim 1 , wherein the first distance and the second distance are along a same axis.

3 . The logic circuit of claim 1 , wherein:

the third diffusion region comprises a first type diffusion region;

the fourth diffusion region comprises a second type diffusion region different from the first type diffusion region;

the first diffusion region comprises the first type diffusion region; and

the second diffusion region comprises the second type diffusion region.

4 . The logic circuit of claim 1 , wherein:

the third diffusion region comprises a first type diffusion region;

the fourth diffusion region comprises a second type diffusion region different from the first type diffusion region;

the first diffusion region comprises the second type diffusion region; and

the second diffusion region comprises the first type diffusion region.

5 . The logic circuit of claim 1 , wherein:

the third diffusion region has a first width between the first side and the second side;

the fourth diffusion region has the first width between the first side and the second side;

the first diffusion region has a second width greater than the first width between the first side and the second side; and

the second diffusion region has the second width between the first side and the second side.

6 . The logic circuit of claim 5 , wherein:

the third diffusion region and the fourth diffusion region have the first width along a first axis;

the first diffusion region and the second diffusion region have the second width along the first axis.

7 . The logic circuit of claim 1 , wherein:

a first outside distance from the first side of the first diffusion region to the second side of the second diffusion region in a first one of the plurality of first devices is the same as a second outside distance from the first side of the first diffusion region to the second side of the second diffusion region in a second one of the plurality of first devices; and

a first inner distance from the first side of the second diffusion region to the second side of the first diffusion region in the first one of the plurality of first devices is different from a second inner distance from the first side of the second diffusion region to the second side of the first diffusion region in the second one of the plurality of first devices.

8 . The logic circuit of claim 5 , wherein:

the third diffusion region has the first width in each of the plurality of second devices; and

the fourth diffusion region has the first width in each of the plurality of second devices.

9 . The logic circuit of claim 5 , wherein:

the second circuit has a first inner distance between the first side of the third diffusion region and the second side of the fourth diffusion region in each of the plurality of second devices.

10 . The logic circuit of claim 5 , wherein:

the second circuit has a first outside distance between the second side of the third diffusion region and the first side of the fourth diffusion region in each of the plurality of second devices.

11 . The logic circuit of claim 5 , wherein:

the first diffusion region and the second diffusion region each have the second width in a first one of the plurality of first devices and a third width, greater than the second width, in a second one of the plurality of first devices.

12 . The logic circuit of claim 5 , wherein:

the first diffusion region and the second diffusion region each have the second width in a first one of the plurality of first devices and have the first width in a second one of the plurality of first devices.

13 . The logic circuit of claim 11 , wherein:

the first diffusion region and the second diffusion region each have the first width in a third one of the plurality of first devices.

14 . The logic circuit of claim 1 , wherein:

each of the third diffusion region, the fourth diffusion region, the first diffusion region, and the second diffusion region comprises at least one nanosheet; and

the plurality of first devices and the plurality of second devices comprise gate-all-around transistors.

15 . The logic circuit of claim 1 , wherein:

a first inner distance from the first side of the second diffusion region to the second side of the first diffusion region in a first one of the plurality of first devices is the same as a second inner distance from the first side of the second diffusion region to the second side of the first diffusion region in a second one of the plurality of first devices; and

a first outside distance in the first one of the plurality of first devices is different from a second outside distance in the second one of the plurality of first devices.

16 . The logic circuit of claim 13 , wherein the plurality of first gates comprises:

a first dummy gate disposed between the first one of the plurality of first devices and the second one of the plurality of first devices; and

a second dummy gate disposed between the first one of the plurality of first devices and the third one of the plurality of first devices.

17 . The logic circuit of claim 1 integrated into an integrated circuit (IC).

18 . The logic circuit of claim 1 , integrated into a device selected from the group consisting of: a set-top box; an entertainment unit; a navigation device; a communications device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; smartphone; a session initiation protocol (SIP) phone; a tablet; a phablet; a server; a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; an automobile; a vehicle component; avionics systems; a drone; and a multicopter.

19 . A semiconductor die, comprising:

a first power rail and a second power rail, each having a longitudinal axis disposed in a first direction and configured to provide a first one of a power supply voltage and a reference voltage;

a third power rail having a longitudinal axis disposed in the first direction and configured to provide a second one of the power supply voltage and the reference voltage; and

a logic circuit comprising:

a first circuit, comprising:

a first diffusion region disposed on a substrate and having a longitudinal axis disposed in the first direction;

a second diffusion region disposed on the substrate and having a longitudinal axis disposed in the first direction;

a plurality of first gates, each having a longitudinal axis disposed in a second direction substantially orthogonal to the first direction; and

a plurality of first devices, each comprising:

a portion of the first diffusion region;

a portion of the second diffusion region; and

one of the plurality of first gates disposed on the portion of the first diffusion region and on the portion of the second diffusion region; and

a second circuit, disposed adjacent to, in the second direction, the first circuit, the second circuit comprising:

a third diffusion region disposed on the substrate and having a longitudinal axis disposed in the first direction;

a fourth diffusion region disposed on the substrate and having a longitudinal axis disposed in the first direction;

a plurality of second gates, each having a longitudinal axis disposed in the second direction; and

a plurality of second devices, each comprising:

a portion of the third diffusion region;

a portion of the fourth diffusion region; and

one of the plurality of second gates disposed on the portion of the third diffusion region and on the portion of the fourth diffusion region;

wherein:

the first circuit is coupled to each of the first power rail and the third power rail;

the second circuit is coupled to each of the second power rail and the third power rail;

each of the third diffusion region, the fourth diffusion region, the first diffusion region, and the second diffusion region comprises a first side and a second side orthogonal to the second direction;

the fourth diffusion region is disposed on the first side of the third diffusion region;

the first diffusion region is disposed on the first side of the second diffusion region; and

a second distance in the second direction from the first side of the fourth diffusion region to the second side of the third diffusion region is less than a first distance in the second direction from the first side of the first diffusion region to the second side of the second diffusion region.

20 . A method of fabricating a logic circuit, the method comprising:

forming a first circuit, comprising:

a first diffusion region disposed on a substrate and having a longitudinal axis disposed in a first direction;

a second diffusion region disposed on the substrate and having a longitudinal axis disposed in the first direction;

a plurality of first gates, each having a first longitudinal axis disposed in a second direction substantially orthogonal to the first direction; and

a plurality of first devices, each comprising:

a portion of the first diffusion region;

a portion of the second diffusion region; and

one of the plurality of first gates disposed on the portion of the first diffusion region and on the portion of the second diffusion region; and

forming a second circuit, disposed adjacent to, in the second direction, the first circuit, the second circuit comprising:

a third diffusion region disposed on the substrate and having a longitudinal axis disposed in the first direction;

a fourth diffusion region disposed on the substrate and having a longitudinal axis disposed in the first direction;

a plurality of second gates, each having a second longitudinal axis disposed in the second direction; and

a plurality of second devices, each comprising:

a portion of the third diffusion region;

a portion of the fourth diffusion region; and

one of the plurality of second gates disposed on the portion of the third diffusion region and on the portion of the fourth diffusion region;

wherein:

each of the third diffusion region, the fourth diffusion region, the first diffusion region, and the second diffusion region comprises a first side and a second side orthogonal to the second direction;

the fourth diffusion region is disposed on the first side of the third diffusion region;

the first diffusion region is disposed on the first side of the second diffusion region; and

a second distance in the second direction from the first side of the fourth diffusion region to the second side of the third diffusion region is less than a first distance in the second direction from the first side of the first diffusion region to the second side of the second diffusion region.