Protection diode matrix for antenna protection
Embodiments are disclosed for a semiconductor structure. The semiconductor structure includes a first nanosheet layer. The first nanosheet layer includes a first channel region, and a heavily doped epitaxial region of a first type. Further, the semiconductor structure includes a second nanosheet layer. The second nanosheet layer includes a second channel region, a heavily doped epitaxial region of a second type disposed above the first nanosheet layer, and a first gate surrounding the first channel region and the second channel region. Additionally, the semiconductor structure includes a protection diode. The protection diode includes a source, a drain, and a second gate. The drain is connected to the first gate, and the second gate is connected to the source.
1 . A semiconductor structure comprising:
a first nanosheet layer, comprising a first channel region, and a heavily doped epitaxial region of a first type;
a second nanosheet layer comprising:
a second channel region;
a heavily doped epitaxial region of a second type disposed above the first nanosheet layer; and
a first gate surrounding the first channel region and the second channel region; and
a protection diode comprising a source, a drain, and a second gate, wherein the drain is connected to the first gate, and wherein the second gate is connected to the source.
2 . The semiconductor structure of claim 1 , wherein the protection diode provides protection against plasma induced damage during a manufacturing process.
3 . The semiconductor structure of claim 2 , wherein the manufacturing process comprises a process prior to removing a substrate of the semiconductor structure.
4 . The semiconductor structure of claim 3 , wherein the manufacturing process comprises a process after removing the substrate of the semiconductor structure.
5 . The semiconductor structure of claim 1 , further comprising a substrate, wherein the substrate is grounded.
6 . The semiconductor structure of claim 5 , wherein the substrate comprises a p-type substrate.
7 . The semiconductor structure of claim 5 , wherein the substrate comprises an n-type substrate.
8 . The semiconductor structure of claim 1 , wherein the first type is an n-type field effect transistor (FET), and wherein the second type is a p-type FET.
9 . The semiconductor structure of claim 1 , wherein the first type is an n-type FET, and wherein the second type is a p-type FET.