Low-stress dielectric layer, planarization method, and low-temperature processing for 3D-integrated electrical device

1 . An electrical device comprising:

a substrate;

a low-stress dielectric layer having a first side and a second side, the low-stress dielectric layer supported by the substrate, wherein the low-stress dielectric layer has a via hole;

an electrically conductive vertical interconnect disposed in the via hole, the electrically conductive vertical interconnect extending towards the second side of the low-stress dielectric layer; and

a fragile material disposed under the second side of the low-stress dielectric layer;

wherein the electrically conductive vertical interconnect is diffusion bonded to another opposing interconnect at a temperature of 150° C. or less;

wherein an upper surface of the electrical device is substantially planar along a plane and includes an upper surface of the electrically conductive vertical interconnect and an upper surface of the low-stress dielectric layer separated by a base layer along the plane;

wherein, prior to diffusion bonding of the electrically conductive vertical interconnect to the other opposing interconnect, the electrically conductive vertical interconnect has a dished surface creating a gap between the electrically conductive vertical interconnect and the other opposing interconnect;

wherein the gap between the electrically conductive vertical interconnect and the other opposing interconnect is closed as a result of the electrically conductive vertical interconnect expanding to fill the gap during diffusion bonding;

wherein the electrically conductive vertical interconnect has a coefficient of thermal expansion that is greater than a coefficient of thermal expansion of the low-stress dielectric layer; and

wherein any stress imparted to the fragile material by the low-stress dielectric layer during diffusion bonding is less than a failure stress of the fragile material.

2 . The electrical device according to claim 1 , wherein the low-stress dielectric layer is depositable at a temperature in a range from 25° C. to 150° C.

3 . The electrical device according to claim 1 , wherein the low-stress dielectric layer surrounds a majority of an axial extent of the electrically conductive vertical interconnect.

4 . The electrical device according to claim 1 , wherein the low-stress dielectric layer is aluminum nitride (AlN x ).

5 . The electrical device according to claim 1 , wherein the low-stress dielectric layer is silicon nitride (SiN x ).

6 . The electrical device according to claim 1 , wherein the electrically conductive vertical interconnect is made of indium.

7 . The electrical device according to claim 1 , wherein the fragile material has a K IC fracture toughness less than 1.0 MPa·m 1/2 .

8 . The electrical device according to claim 1 , further comprising a temperature-sensitive material having a thermal degradation temperature in a range from 100° C. to 250° C.

9 . The electrical device according to claim 8 , wherein the temperature-sensitive material is Hg 1-x Cd x Te having a thermal degradation temperature of 150° C.

10 . The electrical device according to claim 9 , wherein the electrical device is a photoconductor.

11 . The electrical device of claim 1 , wherein the first side of the low-stress dielectric layer faces away from the substrate;

wherein the first side of the low-stress dielectric layer surrounds the via hole and the electrically conductive vertical interconnect; and

wherein at least part of the via hole is along the plane with the upper surface of the electrically conductive vertical interconnect and the upper surface of the low-stress dielectric layer.

12 . A three-dimensional (3D)-integrated electrical device comprising:

a first electrical device; and

a second electrical device comprising a read out integrated circuit;

wherein the first electrical device is bonded and electrically integrated to the second electrical device; and

wherein the first electrical device comprises:

a substrate;

a low-stress dielectric layer having a first side and a second side, the low-stress dielectric layer supported by the substrate, wherein the low-stress dielectric layer has a via hole, and wherein the first side of the low-stress dielectric layer faces away from the substrate;

an electrically conductive vertical interconnect disposed in the via hole, the electrically conductive vertical interconnect extending towards the second side of the low-stress dielectric layer; and

a fragile material disposed under the second side of the low-stress dielectric layer;

wherein the electrically conductive vertical interconnect is diffusion bonded to another opposing interconnect at a temperature of 150° C. or less;

wherein an upper surface of the first electrical device is substantially planar along a plane and includes an upper surface of the electrically conductive vertical interconnect and an upper surface of the low-stress dielectric layer separated by a base layer along the plane;

wherein, prior to diffusion bonding of the electrically conductive vertical interconnect to the other opposing interconnect, the electrically conductive vertical interconnect has a dished surface creating a gap between the electrically conductive vertical interconnect and the other opposing interconnect;

wherein the gap between the electrically conductive vertical interconnect and the other opposing interconnect is closed as a result of the electrically conductive vertical interconnect expanding to fill the gap during diffusion bonding;

wherein the electrically conductive vertical interconnect has a coefficient of thermal expansion that is greater than a coefficient of thermal expansion of the low-stress dielectric layer; and

wherein any stress imparted to the fragile material by the low-stress dielectric layer during diffusion bonding is less than a failure stress of the fragile material.

13 . The 3D-integrated electrical device according to claim 12 , wherein the fragile material has a K IC fracture toughness less than 1.0 MPa·m 1/2 .

14 . The 3D-integrated electrical device according to claim 12 , wherein the first electrical device further comprises a temperature-sensitive material having a thermal degradation temperature in a range from 100° C. to 250° C.

15 . The 3D-integrated electrical device according to claim 14 , wherein the temperature-sensitive material is Hg 1-x Cd x Te having a thermal degradation temperature of 150° C.

16 . A method of fabricating an electrical device, comprising:

forming a fragile material over at least a portion of a substrate;

forming a low-stress dielectric layer having a first side and a second side, the low-stress dielectric layer overlying at least a portion of the fragile material, wherein the first side of the low-stress dielectric layer faces away from the substrate;

forming a via hole in the low-stress dielectric layer; and

forming an electrically conductive vertical interconnect in the via hole, the electrically conductive vertical interconnect extending towards the second side of the low-stress dielectric layer;

wherein the electrically conductive vertical interconnect is diffusion bonded to another opposing interconnect at a temperature of 150° C. or less;

wherein an upper surface of the electrical device is substantially planar along a plane and includes an upper surface of the electrically conductive vertical interconnect and an upper surface of the low-stress dielectric layer separated by a base layer along the plane;

wherein, prior to diffusion bonding of the electrically conductive vertical interconnect to the other opposing interconnect, the electrically conductive vertical interconnect has a dished surface creating a gap between the electrically conductive vertical interconnect and the other opposing interconnect;

wherein the gap between the electrically conductive vertical interconnect and the other opposing interconnect is closed as a result of the electrically conductive vertical interconnect expanding to fill the gap during diffusion bonding;

wherein the electrically conductive vertical interconnect has a coefficient of thermal expansion that is greater than a coefficient of thermal expansion of the low-stress dielectric layer; and

wherein any stress imparted to the fragile material by the low-stress dielectric layer during diffusion bonding is less than a failure stress of the fragile material.

17 . The method according to claim 16 , wherein the low-stress dielectric layer surrounds a majority of an axial extent of the electrically conductive vertical interconnect.

18 . The method according to claim 16 , wherein:

at a time of forming the low-stress dielectric layer, the electrical device includes a thermally-sensitive material having a thermal degradation temperature in a range from 100° C. to 200° C.; and

the low-stress dielectric layer is formed at a temperature equal to or less than the thermal degradation temperature of the thermally-sensitive material.

19 . The method according to claim 18 , wherein the fragile material has a K IC fracture toughness less than 1.0 MPa·m 1/2 .

20 . The method according to claim 18 , wherein:

the thermally-sensitive material is Hg 1-x Cd x Te;

the low-stress dielectric layer is aluminum nitride (AlN x ) or silicon nitride (SiN x ); and

the electrically conductive vertical interconnect is indium.