Method of controlling bow in a semiconductor structure, semiconductor structure, and semiconductor device
A method of controlling bow in a layered semiconductor structure comprises the steps of: providing a layered semiconductor structure comprising a first layer of III-nitride semiconductor material on a substrate, the layered semiconductor structure having a first bow, and forming a porous region of III-nitride semiconductor material over the first layer of III-nitride semiconductor material, in which the layered semiconductor structure comprising the porous region has a second bow different from the first bow. A semiconductor structure having controllable bow comprises a first layer of III-nitride semiconductor material on a substrate, and a porous region of III-nitride semiconductor material over the first layer of III-nitride semiconductor material. The layered semiconductor structure comprising the porous region has a second bow, and the second bow is tunable by tuning a porosity and/or thickness of the porous region.
1 . A method of controlling bow in a layered semiconductor structure, the method comprising the steps of:
providing a layered semiconductor structure comprising a first layer of III-nitride semiconductor material on a substrate, the layered semiconductor structure having a first bow; and
forming a porous region of III-nitride semiconductor material over the first layer of III-nitride semiconductor material, so that an overall porosity of the semiconductor structure positioned on the substrate, including the first layer of III-nitride material and the porous region, is between 5% and 90% porous,
in which the layered semiconductor structure comprising the porous region has a second bow different from the first bow.
2 . The method according to claim 1 , in which the first bow is a concave bow, and in which the second bow is less concave than the first bow.
3 . The method according to claim 1 , in which the first bow is a convex bow, and in which the second bow is less convex than the first bow.
4 . The method according to claim 1 , in which the second bow is between 1% and 80% less than the first bow, or between 3% and 70% less than the first bow, or between 8% and 65% less than the first bow.
5 . The method according to claim 1 , in which the second bow is between 5 μm and 150 μm less than the first bow, or between 10 μm and 100 μm less than the first bow, or between 25 μm and 50 μm less than the first bow.
6 . The method according to claim 1 , in which the overall porosity of the semiconductor structure positioned on the substrate, including the first III-nitride layer and the porous region, is between 10% and 80% porous, or between 20% and 70% porous.
7 . The method according to claim 1 , including the step of tuning the second bow, in which tuning the second bow comprises tuning at least one of the porosity or the thickness of the porous region.
8 . The method according to claim 1 , wherein the tuning the second bow comprises compensating the first bow that results from the substrate and the first layer of III-nitride material having different thermal coefficients of expansion.
9 . The method according to claim 1 , in which the step of forming a porous layer of III-nitride semiconductor material over the first layer of III-nitride semiconductor material comprises depositing an n-doped region of III-nitride material over the first layer of semiconductor material, and electrochemically porosifying the n-doped region of III-nitride material to form the porous region of III-nitride material.
10 . The method according to claim 1 , comprising the step of forming the porous region of III-nitride material by electrochemical porosification through a non-porous layer of III-nitride material, such that the non-porous layer of III-nitride material forms a non-porous intermediate layer over the porous region.
11 . The method according to claim 1 , in which the porous region has a porosity of between 10% and 80% porous, and/or in which the porous region has a thickness of between 100 nm and 10000 nm.
12 . The method according to claim 1 , in which the porous region is a continuous porous layer having a uniform porosity, which extends over the lateral width of the first layer of III-nitride material.
13 . The method according to claim 1 , in which the porous region extends over only a portion of the lateral width of the first layer of III-nitride material.
14 . The method according to claim 13 , in which the porous region is patterned on the first layer.
15 . The method according to claim 1 , in which the porous region of III-nitride material comprises at least one porous layer of III-nitride material.
16 . The method according to claim 15 , in which the porous region of III-nitride material comprises a stack of multiple porous layers of III-nitride material, in which the stack of porous layers is a stack of alternating porous and non-porous layers.
17 . The method according to claim 1 , in which the first III-nitride layer contains one or more layers or stacks of the following in any sequence: GaN, Al x Ga 1-x N in which x=0-1, or In y Ga 1-y N in which y=0-1.
18 . The method according to claim 1 , in which the substrate is one of: sapphire, silicon, silicon carbide, GaN, AlN, InGaN bulk, oxidized & porous silicon or glass/fused silica.
19 . The method of manufacturing a semiconductor device, the method comprising the steps of manufacturing a layered semiconductor structure having a porous region according to claim 1 ; and forming, over the porous region, a semiconductor device structure.
20 . The method according to claim 19 , comprising the step of forming a second layer of III-nitride material over the porous region before forming the semiconductor device structure on the second layer of III-nitride material.
21 . The method according to claim 19 , in which the semiconductor structure is an LED, a mini-LED, a micro-LED, a power electronics device, or an RF electronics device.
22 . A semiconductor structure having controllable bow comprising:
a first layer of III-nitride semiconductor material on a substrate; and
a porous region of III-nitride semiconductor material over the first layer of III-nitride semiconductor material,
in which the layered semiconductor structure comprising the porous region has a second bow, and wherein the second bow is tunable by tuning a porosity and/or thickness of the porous region,
in which an overall porosity of the semiconductor structure positioned on the substrate, including the first III-nitride layer and the porous region, is between 5% and 90% porous.