LED precursor

1 . A method of manufacturing a LED precursor comprising:

forming a monolithic growth stack having a growth surface and comprising a first semiconducting layer, a second semiconducting layer on the first semiconducting layer, and a third semiconducting layer on an opposite side of the second semiconducting layer to the first semiconducting layer; and

forming a monolithic LED stack directly on the growth surface of the monolithic growth stack,

wherein:

a) forming the monolithic growth stack comprises:

forming the first semiconducting layer, the first semiconducting layer comprising a Group III-nitride;

forming the second semiconducting layer on the first semiconducting layer, the second semiconducting layer comprising a first Group III-nitride including a donor dopant such that the second semiconducting layer has a donor density of at least 5×10 18 cm −3 ;

forming the third semiconducting layer on an opposite side of the second semiconducting layer to the first semiconducting layer, wherein the third semiconducting layer provides the growth surface of the monolithic growth stack, the third semiconducting layer comprising a second Group III-nitride different to the first Group-III-nitride such that the third semiconducting layer is formed on the second semiconducting layer under compressive strain; and

selectively removing a portion of the third semiconducting layer from the growth surface through a thickness of the third semiconducting layer such that the growth surface of the monolithic growth stack comprises a mesa surface of third semiconducting layer and a sidewall surface of the third semiconducting layer encircling the mesa surface,

wherein following formation of the third semiconducting layer:

the second semiconducting layer is subjected to a porosity treatment to increase an areal porosity of the second semiconducting layer to at least 15%; and

the third semiconducting layer is heated to a strain relaxing temperature such that the third semiconducting layer relaxes such that an in-plane lattice constant of the mesa surface increases; and

b) forming the monolithic LED stack comprises:

forming a fourth semiconducting layer comprising a Group III-nitride directly on the growth surface of the monolithic growth stack, such that the fourth semiconducting layer covers the mesa surface of the third semiconducting layer;

forming an active layer on the fourth semiconducting layer, the active layer comprising a plurality of quantum well layers, each quantum well layer comprising a Group III-nitride;

forming a p-type semiconducting layer comprising a Group III-nitride on the active layer.

2 . The method according to claim 1 , wherein

the second semiconducting layer comprises GaN; and/or

the third semiconducting layer comprises In X Ga 1-X N, where 0<X≤1.

3 . The method according to claim 1 , wherein each quantum well layer of the active layer comprises In Z Ga 1-Z n, where 0.2<Z≤0.5.

4 . The method according to claim 1 , wherein the second semiconducting layer is subjected to the porosity treatment prior to selectively removing a portion of the third semiconducting layer from the growth surface.

5 . The method according to claim 4 , wherein forming the monolithic growth stack further comprises:

selectively forming a masking layer on the growth surface of the monolithic growth stack, the masking layer comprising an aperture aligned with the mesa surface of the monolithic growth stack.

6 . The method according to claim 5 , wherein the monolithic LED stack is selectively formed on the mesa surface of the monolithic growth stack and not on the growth surface covered by the masking layer.

7 . The method according to claim 1 , wherein the third semiconducting layer is selectively removed such that the growth surface of the monolithic growth stack comprises a surface of the second semiconducting layer.

8 . The method according to claim 1 , wherein forming the monolithic growth stack further comprises:

selectively removing a portion of the second semiconducting layer aligned with the portion of the third semiconducting layer which is selectively removed such that the growth surface of the monolithic growth stack comprises a sidewall surface of the second semiconducting layer.

9 . The method according to claim 8 , wherein the second semiconducting layer is selectively removed such that the sidewall surface of the second semiconducting layer is aligned with the sidewall surface of the third semiconducting layer.

10 . The method according to claim 8 , wherein the second semiconducting layer is selectively removed such that the growth surface comprises a portion of a surface of the first semiconducting layer.

11 . The method according to claim 1 , wherein the fourth semiconducting layer comprises GaN.

12 . The method according to claim 1 , wherein the fourth semiconducting layer is formed on the growth surface to provide an inclined sidewall portion extending from a mesa portion of the fourth semiconducting layer on the mesa surface of the third semiconducting layer towards the second semiconducting layer.

13 . A LED precursor comprising:

a monolithic growth stack having a growth surface; and

a monolithic LED stack provided directly on the growth surface of the monolithic growth stack,

wherein:

a) the monolithic growth stack comprises:

a first semiconducting layer comprising a Group III-nitride;

a second semiconducting layer provided on the first semiconducting layer, the second semiconducting layer comprising a first Group III-nitride including a donor dopant such that the second semiconducting layer has a donor density of at least 5×10 18 cm −3 , wherein the second semiconducting layer has an areal porosity of at least 15% and a first in-plane lattice constant; and

a third semiconducting layer provided on an opposite side of the second semiconducting layer to the first semiconducting layer, the third semiconducting layer comprising a second Group III-nitride different to the first Group-III-nitride,

wherein the monolithic growth stack comprises a mesa structure comprising the third semiconducting layer such that the growth surface comprises a mesa surface of third semiconducting layer and a sidewall surface of the third semiconducting layer encircling the mesa surface, the sidewall surface of the third semiconducting layer inclined relative to the mesa surface,

wherein the mesa surface of the third semiconducting layer has a second in-plane lattice constant which is greater than the first in-plane lattice constant; and

b) the monolithic LED stack comprises:

a fourth semiconducting layer provided directly on the growth surface of the monolithic growth stack, such that the fourth semiconducting layer is formed directly on the mesa surface of the third semiconducting layer and the sidewall surface of the third semiconducting layer;

an active layer provided on the fourth semiconducting layer, the active layer comprising a plurality of quantum well layers, each quantum well layer comprising a Group III-nitride; and

a p-type semiconducting layer comprising a Group III-nitride provided on the active layer.

14 . The LED precursor according to claim 13 , wherein

the second semiconducting layer comprises GaN; and/or

the third semiconducting layer comprises In X Ga 1-X N, where 0<X≤1.

15 . The LED precursor according to claim 13 , wherein each quantum well layer of the active layer comprises In Z Ga 1-Z N, where 0.2<Z≤0.5.

16 . The LED precursor according to claim 13 , wherein the sidewall surface of the third semiconducting layer is inclined in a direction transverse to the mesa surface.

17 . The LED precursor according to claim 13 , wherein the mesa structure extends from the second semiconducting layer such that growth surface comprises the second semiconducting layer.

18 . The LED precursor according to claim 13 , wherein the growth surface of the monolithic growth stack comprises a sidewall surface of the second semiconducting layer aligned with the sidewall surface of the third semiconducting layer.

19 . The LED precursor according to claim 18 , wherein the mesa structure extends from the first semiconducting layer such that the growth surface comprises a portion of a surface of the first semiconducting layer.

20 . The LED precursor according to claim 13 , wherein the fourth semiconducting layer comprises GaN.

21 . The LED precursor according to claim 13 , wherein the fourth semiconducting layer is provided on the growth surface to provide an inclined sidewall portion extending from a mesa portion of the fourth semiconducting layer on the mesa surface of the third semiconducting layer towards the second semiconducting layer.

22 . The LED precursor according to claim 13 , wherein the monolithic growth stack further comprises:

a masking layer provided on the growth surface of the monolithic growth stack, the masking layer comprising an aperture aligned with the mesa surface of the monolithic growth stack.

23 . The LED precursor according to claim 22 , wherein the monolithic LED stack is selectively provided only on the mesa surface of the monolithic growth stack.

24 . The LED according to claim 13 , wherein the LED precursor is a micro LED precursor wherein the monolithic LED stack has a surface area dimension in a plane aligned with the first semiconducting layer of less than 100 μm×100 μm.

25 . The LED array precursor comprising:

a plurality of LED precursors according to claim 13 , the plurality of LED precursors arranged in a two-dimensional array.