Manufacturing method of memory device

Inventors: Chih-Wei Kuo (Tainan City, TW); Chung-Yi Chiu (Tainan City, TW)

Assignee: UNITED MICROELECTRONICS CORP.

H10N50/01 H10B61/00 H10N50/80

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Quick Facts

Patent No.: US 12685025
App. No.: 18/376,840
Granted: Jul 14, 2026
Kind: B2

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Abstract

A manufacturing method of a memory device includes following steps. Memory units are formed on a substrate. Each memory unit includes a first electrode, a second electrode disposed above the first electrode in a vertical direction, and a memory material layer disposed between the first electrode and the second electrode. A conformal spacer layer is formed on the memory units. A non-conformal spacer layer is formed on the conformal spacer layer. A first opening is formed penetrating through a first portion of the non-conformal spacer layer between the memory units in a horizontal direction and a first portion of the conformal spacer layer on the first portion of the conformal spacer layer in the vertical direction. A thickness of a second portion of the non-conformal spacer layer on the second electrode is greater than a thickness of the second portion of the non-conformal spacer layer on the memory material layer.

Claims (30)

1 . A manufacturing method of a memory device, comprising:

forming memory units on a substrate, wherein each of the memory units comprises:

a first electrode;

a second electrode disposed above the first electrode in a vertical direction; and

a memory material layer disposed between the first electrode and the second electrode in the vertical direction;

forming a conformal spacer layer on the memory units, wherein the conformal spacer layer comprises:

a first portion located between the memory units adjacent to each other in a horizontal direction;

a second portion located on a sidewall of the second electrode of each of the memory units; and

a third portion located above the memory units in the vertical direction;

forming a non-conformal spacer layer on the conformal spacer layer, wherein the non-conformal spacer layer comprises:

a first portion located on the first portion of the conformal spacer layer;

a second portion located on the second portion of the conformal spacer layer in the horizontal direction; and

a third portion located above the third portion of the conformal spacer layer in the vertical direction;

forming a spacer layer on the non-conformal spacer layer;

forming a first opening penetrating through the spacer layer, the first portion of the non-conformal spacer layer and the first portion of the conformal spacer layer in the vertical direction, wherein the second portion of the non-conformal spacer layer is formed on the second electrode of each of the memory units and the memory material layer of each of the memory units in the horizontal direction, and a thickness of the second portion of the non-conformal spacer layer on each of the second electrodes in the horizontal direction is greater than a thickness of the second portion of the non-conformal spacer layer on each of the memory material layers in the horizontal direction, wherein the first opening is directly connected with the first portion of the non-conformal spacer layer and the first portion of the conformal spacer layer, a part of the spacer layer is located directly under a part of the non-conformal spacer layer in the vertical direction before the first opening is formed, and the part of the spacer layer is located directly above the first portion of the non-conformal spacer layer in the vertical direction before the first opening is formed; and

forming a second opening penetrating through the spacer layer and the first portion of the non-conformal spacer layer in the vertical direction and exposing the first portion of the conformal spacer layer before the first opening is formed, wherein the second opening is formed by an etching back process performed to the spacer layer and the non-conformal spacer layer, and third portion of the conformal spacer layer is exposed by the etching back process before the first opening is formed.

2 . The manufacturing method of the memory device according to claim 1 , wherein the second portion of the conformal spacer layer is covered by the second portion of the non-conformal spacer layer in the horizontal direction after the first opening is formed.

3 . The manufacturing method of the memory device according to claim 1 , wherein the sidewall of the second electrode of each of the memory units is completely covered by the second portion of the conformal spacer layer in the horizontal direction after the first opening is formed, and the second portion of the conformal spacer layer is completely covered by the second portion of the non-conformal spacer layer in the horizontal direction after the first opening is formed.

4 . The manufacturing method of the memory device according to claim 1 , wherein the third portion of the non-conformal spacer layer and a part of the second portion of the non-conformal spacer layer on each of the memory units form an overhang structure.

5 . The manufacturing method of the memory device according to claim 4 , wherein a width of the third portion of the non-conformal spacer layer on each of the memory units is greater than a width of the second portion of the non-conformal spacer layer on each of the memory units.

6 . The manufacturing method of the memory device according to claim 4 , wherein a thickness of the third portion of the non-conformal spacer layer on each of the memory units is greater than the thickness of the second portion of the non-conformal spacer layer on each of the second electrodes in the horizontal direction and the thickness of the second portion of the non-conformal spacer layer on each of the memory material layers in the horizontal direction.

7 . The manufacturing method of the memory device according to claim 4 , wherein the third portion of the conformal spacer layer is removed by the step of forming the first opening.

8 . The manufacturing method of the memory device according to claim 1 , wherein the third portion of the non-conformal spacer layer is removed by the step of forming the second opening.

9 . The manufacturing method of the memory device according to claim 1 , wherein a material composition of the spacer layer is different from a material composition of the non-conformal spacer layer.

10 . The manufacturing method of the memory device according to claim 1 , wherein a material composition of the conformal spacer layer is different from a material composition of the non-conformal spacer layer.

11 . The manufacturing method of the memory device according to claim 1 , wherein the conformal spacer layer comprises silicon nitride, and the non-conformal spacer layer comprises oxide or silicon carbide.

12 . The manufacturing method of the memory device according to claim 1 , further comprising:

forming a cap layer on the substrate before the conformal spacer layer is formed, wherein the cap layer is located on each of the memory units, and the second portion of the conformal spacer layer covers the sidewall of the second electrode of each of the memory units and a sidewall of the cap layer on each of the memory units after the first opening is formed.

13 . The manufacturing method of the memory device according to claim 12 , wherein a material composition of the cap layer is different from a material composition of the conformal spacer layer.

14 . The manufacturing method of the memory device according to claim 1 , wherein the memory material layer in each of the memory units comprises a magnetic tunnel junction structure.