Phase-change random access memory device and method of forming the same

1 . A memory device, comprising:

a substrate;

a bottom electrode disposed over the substrate;

a top electrode disposed over the bottom electrode; and

a phase change layer disposed between the top electrode and the bottom electrode, wherein the phase change layer is a laminated structure comprising a first layer of phase change material and a second layer of phase change material alternatingly stacked, and the first layer of phase change material is chemically different from the second layer of phase change material, and wherein the first layer of phase change material has a first thickness that is less than a second thickness of the second layer of phase change material; and

a sidewall barrier layer in contact with sidewalls of the phase change layer,

wherein the first layer of phase change material is a doped chalcogenide material containing a metallic dopant element and the second layer of phase change material is an undoped chalcogenide material,

wherein at least a first one of the first layer of phase change material in the laminated structure has a first dopant concentration, and at least a second one of the first layer of phase change material has a second dopant concentration that is different than the first dopant concentration, and

wherein a topmost one of the second layer of phase change material is disposed adjacent to and in contact with the top electrode, and the first layer of phase change material in the laminated structure is disposed on and in contact with the bottom electrode, and

wherein a side surface of the sidewall barrier layer is in contact with a sidewall of the top electrode, and a bottom surface of the sidewall barrier layer is in contact with a top surface of the bottom electrode.

2 . The memory device of claim 1 , wherein the chalcogenide material comprises at least one or more of germanium (Ge), antimony (Sb), tellurium (Te), selenium (Se), and sulfide(S).

3 . The memory device of claim 2 , wherein the doped or undoped chalcogenide material comprises a Ge—Sb—Te (GST) based compound, a Si—Sb—Te based compound, a Ga—Sb—Te based compound, an As—Sb—Te based compound, an Ag—In—Sb—Te (AIST) based compound, a Ge—In—Sb—Te (GIST) based compound, a Ti—Sb—Te based compound, a Ge—Sb based compound, a Ge—Te based compound, a Ga—Sb based compound, a Sb—Te based compound, a Si—Sb based compound, a Se—S based compound, an As—Te based compound, an As—Se based compound, or stoichiometric materials thereof.

4 . The memory device of claim 3 , wherein the doped chalcogenide material further comprises a non-metal dopant element.

5 . The memory device of claim 4 , wherein the non-metal dopant element comprises nitrogen (N), oxygen (O), carbon (C), silicon (Si), boron (B), phosphorus (P), or the like.

6 . The memory device of claim 1 , wherein the first layer of phase change material is a GST based compound doped with tungsten (W), indium (In), gallium (Ga), niobium (Nb), zirconium (Zr), yttrium (Y), molybdenum (Mo), or the like, and the second layer of phase change material is a GST based compound.

7 . The memory device of claim 1 , wherein the first thickness and the second thickness have a ratio (first thickness:second thickness) in a range of about 1:2 to about 1:10.

8 . The memory device of claim 7 , wherein the phase change layer has a third thickness, and the third thickness and the first thickness have a ratio (third thickness:

first thickness) in a range of about 5:1 to about 15:1.

9 . The memory device of claim 1 ,

wherein the sidewall barrier layer comprises a Nitride-Oxide-Nitride (NON) structure.

10 . The memory device of claim 1 , wherein the second layer of phase change material has a RMS roughness in a range of about 0.100 nm to about 0.125 nm.

11 . A memory device, comprising:

a word line disposed in an interconnect-level dielectric layer stack;

a selector disposed over the word line in the interconnect-level dielectric layer stack;

a phase change layer disposed over the selector in the interconnect-level dielectric layer stack, the phase change layer comprising:

a first layer of doped chalcogenide material containing a first dopant element;

a first layer of undoped chalcogenide material disposed above and in contact with the first layer of doped chalcogenide material;

a second layer of doped chalcogenide material containing a second dopant element that is different than the first dopant element, wherein the second layer of doped chalcogenide material is disposed above and in contact with the first layer of undoped chalcogenide material; and

a second layer of undoped chalcogenide material disposed above and in contact with the second layer of doped chalcogenide material;

a sidewall barrier layer in contact with sidewalls of the phase change layer; and

a bit line disposed over the phase change layer in the interconnect-level dielectric layer stack,

wherein the second layer of undoped chalcogenide material is disposed adjacent to the bit line, and the first layer of doped chalcogenide material is disposed on and in contact with a top surface of a second barrier electrode of the selector, and

wherein a top surface of the sidewall barrier layer is in contact with a bottom surface of the bit line, and a bottom surface of the sidewall barrier layer is in contact with the top surface of the second barrier electrode of the selector.

12 . The memory device of claim 11 , wherein the phase change layer further comprises:

a third layer of doped chalcogenide material containing the first dopant element, wherein the third layer of doped chalcogenide material is disposed above and in contact with the second layer of undoped chalcogenide material; and

a third layer of undoped chalcogenide material disposed above and in contact with the third layer of doped chalcogenide material.

13 . The memory device of claim 11 , wherein the first, second, third layers of doped chalcogenide material and the first, second, third layers of undoped chalcogenide material comprise at least one or more of germanium (Ge), antimony (Sb), tellurium (Te), selenium (Se), and sulfide(S).

14 . The memory device of claim 13 , wherein the first, second, third layers of doped chalcogenide material are a GST compound doped with nitrogen (N), oxygen (O), carbon (C), silicon (Si), boron (B), phosphorus (P), or the like.

15 . The memory device of claim 11 , wherein the each of first and second layers of doped chalcogenide material has a first thickness, and each of the first and second layers of undoped chalcogenide material has a second thickness that is at least two times greater than the first thickness.

16 . The memory device of claim 11 , wherein the selector further comprises:

a first barrier electrode;

the second barrier electrode; and

a selector material layer disposed between the first and second barrier electrodes.

17 . The memory device of claim 16 , wherein the first barrier electrode is in contact with the word line, and the second barrier electrode is in contact with the first layer of doped chalcogenide material.

18 . The memory device of claim 11 , further comprising:

a top barrier electrode disposed over the phase change layer

wherein the sidewall barrier layer is in contact with sidewalls of the top barrier electrode.

19 . The memory device of claim 11 , wherein the each of first and second layers of doped chalcogenide material has a first thickness, and each of the first and second layers of undoped chalcogenide material has a second thickness that is greater than the first thickness.

20 . A memory device, comprising:

a word line disposed in an interconnect-level dielectric layer stack;

a bit line disposed over the word line in the interconnect-level dielectric layer stack;

a selector disposed in the interconnect-level dielectric layer stack;

a phase change layer disposed between the world line and the bit line, the phase change layer comprising:

a first layer of doped chalcogenide material containing a first metallic dopant element;

a first layer of undoped chalcogenide material disposed adjacent the first layer of doped chalcogenide material;

a second layer of doped chalcogenide material containing a second metallic dopant element that is different than the first metallic dopant element, and the second layer of doped chalcogenide material is disposed adjacent the first layer of undoped chalcogenide material; and

a second layer of undoped chalcogenide material disposed adjacent the second layer of doped chalcogenide material and the bit line; and

a sidewall barrier layer in contact with sidewalls of the phase change layer,

wherein the first layer of doped chalcogenide material is disposed on and in contact with a top surface of a first barrier electrode of the selector, and

wherein a top surface of the sidewall barrier layer is in contact with a bottom surface of the bit line, and a bottom surface of the sidewall barrier layer is in contact with the top surface of the first barrier electrode of the selector.