Methods of separating semiconductor dies
Methods of separating semiconductor dies are described. The method can separate individual semiconductor dies from a semiconductor wafer without using a blade. The methods include a plasma etch process utilizing metal structures formed on a back side of the wafer as masks to remove a portion of the semiconductor wafer from the back side. The portion removed by the plasma etch process corresponds to the scribe lines between the semiconductor dies. The plasma etch process terminates at a dielectric layer formed on a front side of the wafer. The dielectric layer may be severed to complete the separation process. Moreover, an ultrasonic water jet process may be utilized to remove burrs of the dielectric layer that has been severed.
1 . A method, comprising:
forming a patterned metal layer on a back side of a semiconductor substrate including a plurality of dies on a front side opposite the back side, wherein a scribe region of the semiconductor substrate is uncovered by the patterned metal layer;
applying a plasma etch process configured to remove the scribe region uncovered by the patterned metal layer, wherein a portion of a dielectric layer disposed at the front side of the semiconductor substrate is exposed as a result of applying the plasma etch process;
attaching an adhesive tape to the patterned metal layer;
severing the portion of the dielectric layer by pulling the adhesive tape in opposite directions; and
applying an ultrasonic water jet process configured to remove burrs of the dielectric layer based on severing the portion of the dielectric layer.
2 . The method of claim 1 , wherein the plasma etch process has an etch selectivity configured to preserve the patterned metal layer.
3 . The method of claim 1 , wherein the plasma etch process has an etch selectivity configured to preserve the dielectric layer.
4 . The method of claim 1 , wherein the plasma etch process includes deposition steps and etch steps that alternate with each other.
5 . The method of claim 1 , wherein the dielectric layer includes one or more inter-level metallization layers.
6 . The method of claim 1 , wherein the patterned metal layer includes a plurality of metal structures corresponding to the plurality of dies.
7 . The method of claim 6 , wherein the plasma etch process utilizes the plurality of metal structures as masks that protect the semiconductor substrate.
8 . The method of claim 6 , wherein each one of the metal structures includes at least one edge aligned to an edge of corresponding one of the dies.
9 . The method of claim 1 , wherein applying the plasma etch process forms uneven sidewall profiles of individual dies of the plurality.
10 . The method of claim 9 , wherein the uneven sidewall profiles include a plurality of raised lines substantially parallel to the back side of the semiconductor substrate.
11 . The method of claim 9 , wherein the uneven sidewall profiles are substantially perpendicular to the back side of the semiconductor substrate.
12 . The method of claim 9 , wherein the uneven sidewall profiles include ribbed surfaces, undulating surfaces, surfaces with ridges, surfaces with crests and troughs, or a combination thereof.
13 . The method of claim 1 , wherein the ultrasonic water jet process includes applying ultrasonic oscillation and pressure to a stream of water, the ultrasonic oscillation ranging approximately between 500 to 3,000 hertz (Hz) and the pressure ranging approximately between 10 to 40 pounds per square inch (psi).
14 . The method of claim 1 , further comprising:
thinning the semiconductor substrate from the back side prior to forming the patterned metal layer on the back side of the semiconductor substrate.
15 . A method, comprising:
forming a patterned conductive layer on a back side of a semiconductor substrate including a plurality of dies at a front side opposite the back side, wherein a scribe area of the semiconductor substrate is uncovered by the patterned conductive layer;
removing the scribe area of the semiconductor substrate, wherein a portion of a dielectric layer located at the front side of the semiconductor substrate is exposed from the back side as a result of removing the scribe area of the semiconductor substrate;
attaching a tape to the patterned conductive layer;
breaking the portion of the dielectric layer by expanding the tape attached to the patterned conductive layer; and
removing burrs of the portion of the dielectric layer that has been broken.
16 . The method of claim 15 , wherein the patterned conductive layer includes a plurality of metal structures corresponding to the plurality of dies.
17 . The method of claim 16 , wherein each one of the metal structures includes at least one edge aligned to an edge of corresponding one of the dies.
18 . The method of claim 15 , wherein removing the scribe area of the semiconductor substrate includes applying a plasma process having deposition steps and etch steps that alternate with each other.
19 . The method of claim 15 , wherein removing the scribe area of the semiconductor substrate forms uneven sidewall profiles of individual dies of the plurality.
20 . The method of claim 19 , wherein the uneven sidewall profiles include a plurality of raised lines substantially parallel to the back side of the semiconductor substrate.
21 . The method of claim 19 , wherein the uneven sidewall profiles are substantially perpendicular to the back side of the semiconductor substrate.
22 . The method of claim 15 , wherein the portion of the dielectric layer exposed includes one or more inter-level metallization layers.
23 . The method of claim 15 , wherein removing the burrs includes utilizing an ultrasonic water jet process that applies ultrasonic oscillation and pressure to a stream of water, the ultrasonic oscillation ranging approximately between 500 to 3,000 hertz (Hz) and the pressure ranging approximately between 10 to 40 pounds per square inch (psi).
24 . The method of claim 15 , further comprising:
thinning the semiconductor substrate from the back side prior to forming the patterned conductive layer on the back side of the semiconductor substrate.