Pressure puck diagnostic wafer

1 . A diagnostic wafer for a semiconductor processing chamber, comprising:

a wafer body defining a plurality of discrete and spaced apart recesses; and

a plurality of pucks, the plurality of pucks comprising:

at least one data logging puck positionable within one of the plurality of recesses;

at least one battery puck positionable within one of the plurality of recesses; and

at least one sensor puck positionable within one of the plurality of recesses;

wherein:

each recess of the plurality of recesses contains a single puck of the plurality of pucks and the at least one data logging puck, the at least one battery puck, and the at least one sensor puck are each insertable within any of the plurality of recesses; and

a top surface of the at least one sensor puck is exposed through a top surface of the diagnostic wafer.

2 . The diagnostic wafer for a semiconductor processing chamber of claim 1 , wherein:

each of the at least one battery puck comprises a plurality of batteries.

3 . The diagnostic wafer for a semiconductor processing chamber of claim 1 , wherein:

each of the at least sensor puck comprises at least one sensor selected from the group consisting of:

temperature sensors, pressure sensors, retarding field energy analyzers (RFEA), plasma probes, optical emission probes for plasma diagnostics, visible light sensors, IR light sensors/cameras.

4 . The diagnostic wafer for a semiconductor processing chamber of claim 1 , wherein:

at least some of the at least one data logging puck, the at least one battery puck, and the at least one sensor puck comprise an alignment mechanism that properly orient a respective puck within one of the plurality of recesses.

5 . The diagnostic wafer for a semiconductor processing chamber of claim 1 , wherein:

the wafer further comprises a bus that couples each of the at least one battery puck, the at least one sensor puck, and the at least one data logging puck.

6 . The diagnostic wafer for a semiconductor processing chamber of claim 1 , wherein:

at least some of the at least one data logging puck, the at least one battery puck, and the at least one sensor puck comprise a ceramic coating.

7 . The diagnostic wafer for a semiconductor processing chamber of claim 1 , wherein:

the at least one sensor puck comprises a plurality of sensor pucks; and

each of the plurality of sensor pucks comprises a same type of sensor.

8 . The diagnostic wafer for a semiconductor processing chamber of claim 1 , wherein:

the at least one sensor puck comprises a plurality of sensor pucks; and

at least some of the plurality of sensor pucks comprise a different type of sensor.

9 . A diagnostic wafer for a semiconductor processing chamber, comprising:

a wafer body defining a plurality of discrete and spaced apart recesses, each of the plurality of recesses comprising a plurality of electrical contacts, wherein the wafer body comprises a connection circuit that electrically couples the plurality of electrical contacts of each of the plurality of recesses with the plurality of electrical contacts of at least one other of the plurality of recesses; and

a plurality of pucks, the plurality of pucks comprising:

a plurality of battery pucks positionable within one of the plurality of recesses; and

a plurality of sensor pucks positionable within one of the plurality of recesses;

wherein:

each recess of the plurality of recesses contains a single puck and the plurality of battery pucks and the plurality of sensor pucks are each insertable within any of the plurality of recesses; and

a top surface of each of the plurality of sensor pucks is exposed through a top surface of the diagnostic wafer.

10 . The diagnostic wafer for a semiconductor processing chamber of claim 9 , wherein:

at least one of the plurality of battery pucks comprises a status LED.

11 . The diagnostic wafer for a semiconductor processing chamber of claim 9 , wherein:

at least one of the plurality of sensor pucks comprises a status LED.

12 . The diagnostic wafer for a semiconductor processing chamber of claim 9 , wherein:

one or both of the wafer body and the plurality of sensor pucks comprise a wireless antenna.

13 . The diagnostic wafer for a semiconductor processing chamber of claim 9 , wherein:

a thickness of each of the plurality of sensor pucks matches a depth of each of the plurality of recesses.

14 . A method of monitoring conditions within a semiconductor processing chamber, the method comprising:

positioning a diagnostic wafer on a substrate support of a semiconductor processing chamber, the diagnostic wafer comprising:

a wafer body defining a plurality of discrete and spaced apart recesses; and

a plurality of pucks, the plurality of pucks comprising:

at least one data logging puck positionable within one of the plurality of recesses;

at least one battery puck positionable within one of the plurality of recesses; and

at least one sensor puck positionable within one of the plurality of recesses,

wherein:

each recess of the plurality of recesses contains a single puck of the plurality of pucks and the at least one data logging puck, the at least one battery puck, and the at least one sensor puck are each insertable within any of the plurality of recesses; and

a top surface of the at least one sensor puck is exposed through a top surface of the diagnostic wafer;

performing one or more processing operations within the semiconductor processing chamber; and

monitoring at least one operating condition within the semiconductor processing chamber using the at least one sensor puck.

15 . The method of monitoring conditions within a semiconductor processing chamber of claim 14 , further comprising:

recording data associated with the at least one operating condition using the at least one data logging puck.

16 . The method of monitoring conditions within a semiconductor processing chamber of claim 14 , further comprising:

transmitting data associated with the at least one operating condition to a computing device outside the semiconductor processing chamber.

17 . The method of monitoring conditions within a semiconductor processing chamber of claim 14 , wherein:

the at least one operating condition comprises one or more selected from the group consisting of a temperature within the semiconductor processing chamber, a pressure within the semiconductor processing chamber, an ion and electron current within the semiconductor processing chamber, an ion and electron energy within the semiconductor processing chamber, a plasma potential within the semiconductor processing chamber, and a light emission within the semiconductor processing chamber.

18 . The method of monitoring conditions within a semiconductor processing chamber of claim 14 , wherein:

the at least one battery puck is operated in a pulse mode.

19 . The diagnostic wafer for a semiconductor processing chamber of claim 1 , wherein:

at least a subset of the plurality of pucks are removably coupled within a respective recess of the plurality of recesses.

20 . The diagnostic wafer for a semiconductor processing chamber of claim 1 , wherein:

the top surface of the at least one sensor puck is configured to remain exposed through the top surface of the diagnostic wafer when inserted within a chamber environment.