IP Library Granted Patent US 12685087
Granted Patent B2
US 12685087 · App. 18/072,730 · Granted Jul 14, 2026

Plasma diced wafers and methods thereof

Inventors: Dzafir Bin Mohd Shariff (Singapore, SG); Il Kwon Shim (Singapore, SG); Enrique E. Sarile, Jr. (Singapore, SG); Jackson Fernandez Rosario (Singapore, SG); Ronnie M. De Villa (Singapore, SG); Chan Loong Neo (Singapore, SG)
Assignee: UTAC HEADQUARTERS PTE. LTD.
H10P72/7402B23K26/38H10P50/242H10P54/00H10P72/7416
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Quick Facts
Patent No.
US 12685087
App. No.
18/072,730
Granted
Jul 14, 2026
Kind
B2
Abstract

Reliable plasma dicing of a wafer with a die attach film (DAF) to the bottom wafer surface to singulate it into individual dies is disclosed. Laser processing is employed to form mask openings in a passivation stack of a processed wafer to serve as a dicing mask. A combination of plasma dicing and laser cutting is employed. Plasma is employed to etch the wafer while laser is employed to cut the DAF.

Claims (36)

1 . A method of forming devices comprising:

providing a processed wafer processed with a plurality of devices arranged in rows and columns separated by first and second saw streets in first and second orthogonal directions, wherein the processed wafer includes

a wafer having opposing inactive and active wafer surfaces,

a BEOL dielectric having opposing top and bottom BEOL dielectric surfaces, wherein the bottom surface is disposed on the active wafer surface,

a passivation layer having opposing top and bottom passivation surfaces, wherein the bottom passivation surface is disposed on the top BEOL dielectric surface, the passivation layer includes passivation openings to expose the top BEOL dielectric surface for plasma dicing the wafer;

a die attach film (DAF) attached to the inactive wafer surface;

plasma etching the processed wafer exposed by the passivation openings, wherein the plasma etching etches the BEOL dielectric and an upper portion of the wafer to form sidewall surfaces, wherein the plasma etching leaves a remaining lower portion of the wafer and the DAF; and

laterally stretching the wafer to singulate the wafer into devices by breaking the remaining lower portion of the wafer and the DAF, wherein

the sidewall surfaces form a first device sidewall portion of the devices, and

the remaining lower portion of the wafer and the DAF forms a second device sidewall portion of the devices.

2 . The method of claim 1 wherein the second device sidewall portion comprises:

a wafer foot extension; and

a vertical flat wafer sidewall surface, the wafer foot extension extends the vertical flat wafer sidewall surface beyond the first device sidewall portion of the devices.

3 . The method of claim 2 wherein the second device sidewall portion further comprises a vertical flat DAF sidewall surface, the vertical flat DAF sidewall surface is aligned with the vertical flat wafer sidewall surface.

4 . The method of claim 3 wherein the vertical flat DAF sidewall surface and the vertical flat wafer sidewall surface comprise force separated surfaces.

5 . The method of claim 1 comprises a third device sidewall portion, the third device sidewall portion is defined by side passivation side surfaces, the side passivation side surfaces comprise vertical flat passivation sidewall surfaces.

6 . A method of forming devices comprising:

providing a processed wafer processed with a plurality of devices arranged in rows and columns separated by first and second saw streets in first and second orthogonal directions, wherein the processed wafer includes

a wafer having opposing inactive and active wafer surfaces,

a BEOL dielectric having opposing top and bottom BEOL dielectric surfaces, wherein the bottom BEOL dielectric surface is disposed on the active wafer surface,

a passivation layer having opposing top and bottom passivation surfaces, wherein the bottom passivation surface is disposed on the top BEOL dielectric surface, the passivation layer includes passivation openings to expose the top BEOL dielectric surface for plasma dicing the wafer;

a die attach film (DAF) attached to the inactive wafer surface;

plasma etching the processed wafer exposed by the passivation openings, wherein the plasma etching etches the BEOL dielectric and the wafer to form scalloped device sidewall surfaces; and

laser cutting the DAF in the passivation openings, wherein laser cutting causes the DAF to creep up to cover a lower portion of the scalloped device sidewall surfaces.

7 . The method of claim 6 wherein the laser cutting partially cuts the DAF.

8 . The method of claim 7 further comprises laterally stretching the wafer with the partially cut DAF to singulate the wafer into devices, wherein the DAF forms a second device sidewall portion.

9 . The method of claim 6 wherein the laser cutting partially cuts the DAF below the inactive wafer surface.

10 . The method of claim 6 wherein the laser fully cuts the DAF to singulate the processed wafer into devices.

11 . The method of claim 8 wherein the second device sidewall portion comprises:

a DAF foot extension; and

a vertical flat DAF sidewall surface, wherein the DAF foot extension extends the vertical flat DAF sidewall surface beyond the lower portion of the scalloped device sidewall surfaces.

12 . The method of claim 6 wherein the passivation layer comprises vertical flat passivation sidewall surfaces.

13 . The method of claim 1 wherein the sidewall surfaces comprise scalloped device sidewall surfaces.

14 . The method of claim 1 wherein the lower portion of the wafer has a thickness of about 5-50% of the wafer thickness.

15 . The method of claim 1 wherein the passivation openings comprise laser etched passivation openings.

16 . The method of claim 6 wherein the passivation openings comprise laser etched passivation openings.