Multi-function etching sacrificial layers to protect three-dimensional dummy fins in semiconductor devices

1 . A method of manufacturing a semiconductor device, the method comprising:

forming mutually parallel three-dimensional (3D) conductive channels coated with a conformal sacrificial layer, the 3D conductive channels coated with the conformal sacrificial layer being formed on a semiconductor substrate;

depositing a dielectric material to fill spaces between the 3D conductive channels coated with the conformal sacrificial layer, wherein the depositing of the dielectric material includes:

forming a basal dielectric layer of the dielectric material doped with boron, lithium, or beryllium over the conformal sacrificial layer coating the 3D conductive channels, the basal dielectric layer not filling the spaces between the 3D conductive channels, and

after forming the basal dielectric layer, depositing the dielectric material without boron, lithium, or beryllium doping to fill the spaces between the 3D conductive channels with the dielectric material not doped with boron, lithium, or beryllium;

performing chemical mechanical polishing (CMP) to remove a top portion of the deposited dielectric material and to expose tops of the 3D conductive channels; and

after the CMP, removing the conformal sacrificial layer coating the 3D conductive channels by etching to form 3D dielectric features spaced apart from the 3D conductive channels and comprising the deposited dielectric material.

2 . The method of claim 1 wherein the forming of the basal dielectric layer includes:

depositing an initial layer of the dielectric material without boron, lithium, or beryllium doping, the initial layer not filling the spaces between the 3D conductive channels; and

implanting boron, lithium, or beryllium atoms into the initial layer to form the basal dielectric layer of the dielectric material doped with boron, lithium, or beryllium.

3 . The method of claim 1 wherein the basal dielectric layer is doped with boron, lithium, or beryllium at a concentration of 10 13 to 10 18 atoms/cm 3 .

4 . The method of claim 1 wherein the basal dielectric layer is doped with boron.

5 . The method of claim 1 wherein the deposited dielectric material is Si 1-x-y C x N y where 0≤x≤1 and 0≤y≤1.

6 . The method of claim 1 wherein the conformal sacrificial layer coating the 3D conductive channels comprises a silicon nitride material.

7 . The method of claim 1 wherein the depositing of the dielectric material comprises depositing the dielectric material by chemical vapor deposition (CVD) and includes doping the basal dielectric layer with boron during the CVD by flowing a precursor comprising B, B 2 H 6 , or BF 4 .

8 . The method of claim 1 further comprising:

fabricating transistors on the semiconductor substrate, the transistors including transistor channels formed from the 3D conductive channels.

9 . The method of claim 8 wherein the transistors further include transistor gates with gate isolation structures.

10 . The method of claim 8 wherein the transistors are fin field-effect transistors (finFETs), the 3D conductive channels are fins of the finFETs, and the 3D dielectric features are dummy fins.

11 . The method of claim 1 wherein the basal dielectric layer is doped with lithium.

12 . The method of claim 1 wherein the basal dielectric layer is doped with beryllium.

13 . A method of manufacturing a semiconductor device, the method comprising:

forming three-dimensional (3D) conductive channels disposed on a semiconductor substrate; and

forming 3D dielectric features spaced apart from the 3D conductive channels and comprising Si 1-x-y C x N y dielectric material where 0≤x≤1 and 0≤y≤1;

wherein all of the Si 1-x-y C x N y dielectric material of the 3D dielectric features is doped with boron, lithium, or beryllium.

14 . The method of claim 13 wherein:

all of the Si 1-x-y C x N y dielectric material of the 3D dielectric features is doped with boron, lithium, or beryllium at a concentration of 10 13 to 10 18 atoms/cm 3 .

15 . The method of claim 13 wherein the 3D conductive channels are fins of fin field-effect transistors (finFETs), and the 3D dielectric features are dummy fins.

16 . The method of claim 13 wherein all of the Si 1-x-y C x N y dielectric material of the 3D dielectric features is doped with boron.

17 . The method of claim 13 wherein all of the Si 1-x-y C x N y dielectric material of the 3D dielectric features is doped with lithium.

18 . The method of claim 13 wherein all of the Si 1-x-y C x N y dielectric material of the 3D dielectric features is doped with beryllium.

19 . A method of manufacturing a semiconductor device, the method comprising:

forming fins coated with a conformal sacrificial layer, the fins coated with the conformal sacrificial layer being formed on a semiconductor substrate;

depositing a dielectric material to fill spaces between the fins coated with the conformal sacrificial layer, wherein a portion or all of the deposited dielectric material is doped with boron at a concentration of 10 13 to 10 18 atoms/cm 3 , wherein one of: (i) all of the deposited dielectric material is doped with boron, or (ii) only an initial layer of the dielectric material is doped with boron;

performing planarization to remove a top portion of the deposited dielectric material and to expose tops of the fins;

after the planarization, removing the conformal sacrificial layer coating the fins by etching to form dummy fins spaced apart from the fins and comprising the deposited dielectric material; and

fabricating fin field-effect transistors (finFETs) having the fins as conductive channels.

20 . The method of claim 19 wherein:

the deposited dielectric material is Si 1-x-y C x N y where 0≤x≤1 and 0≤y≤1; and

the conformal sacrificial layer coating the fins comprises a silicon nitride material.