IP Library Granted Patent US 12685099
Granted Patent B2
US 12685099 · App. 18/105,801 · Granted Jul 14, 2026

Method of multi-layer die stacking with die-to-wafer bonding

Inventors: Guan Huei See (Singapore, SG); Jinho An (San Jose, CA); Arvind Sundarrajan (Singapore, SG)
Assignee: Applied Materials Inc.
H10W20/023H10W74/014H10W72/0198H10W80/312H10W80/327
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Quick Facts
Patent No.
US 12685099
App. No.
18/105,801
Granted
Jul 14, 2026
Kind
B2
Abstract

Embodiments of methods of die stacking are provided herein. In some embodiments, a method of die stacking with die-to-wafer bonding includes: bonding a plurality of first dies to a substrate via a hybrid bonding process; performing a selective silicon (Si) thinning process to reduce a thickness of the plurality of first dies that are bonded to form a plurality of thinned first dies; passivating the plurality of thinned first dies to form a plurality of passivated thinned first dies to protect the plurality of thinned first dies; filling gaps between adjacent dies of the plurality of thinned first dies with a first fill material, wherein the plurality of passivated thinned first dies and the first fill material together form a first layer; and forming a plurality of first conductive vias through the first layer to the substrate.

Claims (53)

1 . A method of die stacking with die-to-wafer bonding, comprising:

bonding a plurality of first dies to a substrate via a hybrid bonding process;

performing a selective silicon (Si) thinning process to reduce a thickness of the plurality of first dies that are bonded to form a plurality of thinned first dies;

passivating the plurality of thinned first dies to form a plurality of passivated thinned first dies to protect the plurality of thinned first dies;

filling gaps between adjacent dies of the plurality of thinned first dies with a first fill material, wherein the plurality of passivated thinned first dies and the first fill material together form a first layer;

forming a plurality of first conductive vias through the first layer to the substrate; and further comprising at least one of:

(a) planarizing the plurality of thinned first dies and first fill material prior to forming the plurality of first conductive vias;

or

(b) bonding a plurality of second dies to the first layer via a hybrid bonding process;

performing a selective silicon (Si) thinning process to reduce a thickness of the plurality of second dies that are bonded to form a plurality of thinned second dies;

passivating the plurality of thinned second dies to form a plurality of passivated thinned second dies to protect the plurality of thinned second dies;

filling gaps between adjacent dies of the plurality of thinned second dies with a second fill material, wherein the plurality of passivated thinned second dies and the second fill material together form a second layer; and

forming a plurality of second conductive vias through the second layer, wherein the plurality of second conductive vias are aligned with the plurality of first conductive vias.

2 . The method of claim 1 , wherein forming the plurality of first conductive vias is performed as a through-silicon-via (TSV) process where the first conductive vias extend through the plurality of first dies.

3 . The method of claim 1 , wherein forming the plurality of first conductive vias is performed as a through-dielectric-via (TDV) process where the first conductive vias extend through the first fill material and not through the plurality of first dies.

4 . The method of claim 1 , wherein reducing the thickness of the plurality of first dies comprises thinning the plurality of first dies to a thickness of 2 to about 12 microns.

5 . The method of claim 1 , wherein the first fill material comprises essentially of silicon oxide, silicon dioxide, epoxy mold compound, or polymer.

6 . The method of claim 1 , wherein the plurality of thinned first dies are passivated with a layer of silicon nitride (SiN) or silicon carbonitride (SiCN).

7 . The method of claim 1 , wherein passivating the plurality of thinned first dies is performed in a chemical vapor deposition (CVD) chamber, and wherein bonding the plurality of first dies is performed in a bonding chamber.

8 . A non-transitory computer readable medium that contains instructions that, when executed by one or more processors, perform a method of die stacking with die-to-wafer bonding, comprising:

bonding a plurality of first dies to a substrate via a hybrid bonding process;

performing a selective silicon (Si) thinning process to reduce a thickness of the plurality of first dies that are bonded to form a plurality of thinned first dies;

passivating the plurality of thinned first dies to form a plurality of passivated thinned first dies to protect the plurality of thinned first dies;

filling gaps between adjacent dies of the plurality of thinned first dies with a first fill material, wherein the plurality of passivated thinned first dies and the first fill material together form a first layer;

forming a plurality of first conductive vias through the first layer to the substrate; and further comprising at least one of:

(a) planarizing the plurality of thinned first dies and first fill material prior to forming the plurality of first conductive vias;

or

(b) bonding a plurality of second dies to the first layer via a hybrid bonding process;

performing a selective silicon (Si) thinning process to reduce a thickness of the plurality of second dies that are bonded to form a plurality of thinned second dies;

passivating the plurality of thinned second dies to form a plurality of passivated thinned second dies to protect the plurality of thinned second dies;

filling gaps between adjacent dies of the plurality of thinned second dies with a second fill material comprising an organic dielectric material, wherein the plurality of passivated thinned second dies and the second fill material together form a second layer; and

forming a plurality of second conductive vias through the second layer, wherein the plurality of second conductive vias are aligned with the plurality of first conductive vias.

9 . The non-transitory computer readable medium of claim 8 , wherein forming the plurality of first conductive vias is performed as a through-silicon-via (TSV) process where the first conductive vias extend through the plurality of first dies.

10 . The non-transitory computer readable medium of claim 8 , wherein forming the plurality of first conductive vias is performed as a through-dielectric-via (TDV) process where the first conductive vias extend through the first fill material.

11 . A method of die stacking with die-to-wafer bonding, comprising:

forming a plurality of stacked layers on a substrate, wherein forming each stacked layer in the plurality of stacked layers, comprises:

bonding a plurality of dies to an underlayer via a hybrid bonding process, wherein the underlayer is the substrate or one of the plurality of stacked layers;

performing a selective silicon (Si) thinning process to reduce a thickness of the plurality of dies that are bonded to form a plurality of thinned dies;

passivating the plurality of thinned dies to protect the plurality of thinned dies;

filling gaps between adjacent dies of the plurality of thinned dies with a fill material, wherein the passivated plurality of thinned dies and the fill material together form a first layer;

forming a plurality of first conductive vias extending through the plurality of stacked layers via at least one of the fill material or the plurality of thinned dies; and further comprising at least one of:

(a) planarizing the plurality of thinned dies and the fill material prior to forming the plurality of first conductive vias;

or

(b) bonding a plurality of second dies to the first layer via a hybrid bonding process;

performing a selective silicon (Si) thinning process to reduce a thickness of the plurality of second dies that are bonded to form a plurality of thinned second dies;

passivating the plurality of thinned second dies to form a plurality of passivated thinned second dies to protect the plurality of thinned second dies;

filling gaps between adjacent dies of the plurality of thinned second dies with a second fill material comprising an organic dielectric material, wherein the plurality of passivated thinned second dies and the second fill material together form a second layer; and

forming a plurality of second conductive vias through the second layer, wherein the plurality of second conductive vias are aligned with the plurality of first conductive vias.

12 . The method of claim 11 , wherein forming the plurality of first conductive vias is performed as a through-silicon-via (TSV) process where the first conductive vias extend through the plurality of thinned dies.

13 . The method of claim 11 , wherein forming the plurality of first conductive vias is performed as a through-dielectric-via (TDV) process where the first conductive vias extend through the fill material and not through the plurality of thinned dies.

14 . The method of claim 13 , further comprising forming bond pads that are electrically coupled to the plurality of first conductive vias.

15 . The method of claim 11 , wherein the plurality of dies have memory cells.

16 . The method of claim 11 , wherein the plurality of dies have a thickness of 40 to 150 micrometers, and the plurality of thinned dies have a thickness of 2 to 12 micrometers.